Re: [PATCH] x86: entry: flush the cache if syscall error

[Jann Horn]

On Fri, Oct 12, 2018 at 11:41 AM Samuel Neves <sneves@xxxxxxxxx> wrote:
>
> On Thu, Oct 11, 2018 at 8:25 PM Andy Lutomirski <luto@xxxxxxxxxx> wrote:
> > What exactly is this trying to protect against?  And how many cycles
> > should we expect L1D_FLUSH to take?
>
> As far as I could measure, I got 1660 cycles per wrmsr 0x10b, 0x1 on a
> Skylake chip, and 1220 cycles on a Skylake-SP.

Is that with L1D mostly empty, with L1D mostly full with clean lines,
or with L1D full of dirty lines that need to be written back?