[PATCH 4.14 20/41] PCI: dwc: Fix scheduling while atomic issues

From: Greg Kroah-Hartman
Date: Thu Oct 18 2018 - 14:00:27 EST


4.14-stable review patch. If anyone has any objections, please let me know.

------------------

From: Jisheng Zhang <Jisheng.Zhang@xxxxxxxxxxxxx>

[ Upstream commit 9024143e700f89d74b8cdaf316a3499d74fc56fe ]

When programming the inbound/outbound ATUs, we call usleep_range() after
each checking PCIE_ATU_ENABLE bit. Unfortunately, the ATU programming
can be executed in atomic context:

inbound ATU programming could be called through
pci_epc_write_header()
=>dw_pcie_ep_write_header()
=>dw_pcie_prog_inbound_atu()

outbound ATU programming could be called through
pci_bus_read_config_dword()
=>dw_pcie_rd_conf()
=>dw_pcie_prog_outbound_atu()

Fix this issue by calling mdelay() instead.

Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support")
Fixes: d8bbeb39fbf3 ("PCI: designware: Wait for iATU enable")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@xxxxxxxxxxxxx>
[lorenzo.pieralisi@xxxxxxx: commit log update]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Acked-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/pci/dwc/pcie-designware.c | 8 ++++----
drivers/pci/dwc/pcie-designware.h | 3 +--
2 files changed, 5 insertions(+), 6 deletions(-)

--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -138,7 +138,7 @@ static void dw_pcie_prog_outbound_atu_un
if (val & PCIE_ATU_ENABLE)
return;

- usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ mdelay(LINK_WAIT_IATU);
}
dev_err(pci->dev, "outbound iATU is not being enabled\n");
}
@@ -181,7 +181,7 @@ void dw_pcie_prog_outbound_atu(struct dw
if (val & PCIE_ATU_ENABLE)
return;

- usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ mdelay(LINK_WAIT_IATU);
}
dev_err(pci->dev, "outbound iATU is not being enabled\n");
}
@@ -239,7 +239,7 @@ static int dw_pcie_prog_inbound_atu_unro
if (val & PCIE_ATU_ENABLE)
return 0;

- usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ mdelay(LINK_WAIT_IATU);
}
dev_err(pci->dev, "inbound iATU is not being enabled\n");

@@ -285,7 +285,7 @@ int dw_pcie_prog_inbound_atu(struct dw_p
if (val & PCIE_ATU_ENABLE)
return 0;

- usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
+ mdelay(LINK_WAIT_IATU);
}
dev_err(pci->dev, "inbound iATU is not being enabled\n");

--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -28,8 +28,7 @@

/* Parameters for the waiting for iATU enabled routine */
#define LINK_WAIT_MAX_IATU_RETRIES 5
-#define LINK_WAIT_IATU_MIN 9000
-#define LINK_WAIT_IATU_MAX 10000
+#define LINK_WAIT_IATU 9

/* Synopsys-specific PCIe configuration registers */
#define PCIE_PORT_LINK_CONTROL 0x710