Re: [PATCH v2 1/3] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

[Chen-Yu Tsai]

On Mon, Nov 5, 2018 at 3:49 PM Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> wrote:
>
> MUX bits for MMC clock register range are 25:24 where 24 is shift
> and 2 is width So fix the width number from 3 to 2.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx>

Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxx>

However, given that most of the other module clocks have bits 26:24 as
their mux bits, and the mmc clocks use 3 bits to denote the values and
corresponding clock parents, I would have appreciated you actually doing
tests to confirm which of these errors is the actual error, and not just
say "the user manual says so", because it is not always completely correct.