Re: [PATCH v2 1/3] PCI: dwc: allow to limit registers set length

[Lucas Stach]

Am Dienstag, den 20.11.2018, 14:27 +0100 schrieb Stefan Agner:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_own_conf() do not read/write beyond that point.
> 
> Signed-off-by: Stefan Agner <stefan@xxxxxxxx>

FWIW:

Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>

> ---
> Âdrivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++
> Âdrivers/pci/controller/dwc/pcie-designware.hÂÂÂÂÂÂ| 1 +
> Â2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 29a05759a294..b422538ee0bb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -29,6 +29,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> > Â		return pp->ops->rd_own_conf(pp, where, size, val);
> Â
> > Â	pci = to_dw_pcie_from_pp(pp);
> > +	if (pci->dbi_length && where + size > pci->dbi_length)
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> > Â	return dw_pcie_read(pci->dbi_base + where, size, val);
> Â}
> Â
> @@ -41,6 +43,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
> > Â		return pp->ops->wr_own_conf(pp, where, size, val);
> Â
> > Â	pci = to_dw_pcie_from_pp(pp);
> > +	if (pci->dbi_length && where + size > pci->dbi_length)
> > +		return PCIBIOS_BAD_REGISTER_NUMBER;
> > Â	return dw_pcie_write(pci->dbi_base + where, size, val);
> Â}
> Â
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 9f1a5e399b70..5be5f369abf2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -215,6 +215,7 @@ struct dw_pcie {
> > > Â	struct device		*dev;
> > > Â	void __iomem		*dbi_base;
> > > Â	void __iomem		*dbi_base2;
> > > +	int			dbi_length;
> > > Â	u32			num_viewport;
> > > Â	u8			iatu_unroll_enabled;
> > > Â	struct pcie_port	pp;