Re: [PATCH v2 0/3] Mark clocks as critical for MT6797

[Matthias Brugger]

On 30/11/2018 07:47, Stephen Boyd wrote:
> Quoting matthias.bgg@xxxxxxxxxx (2018-11-16 10:08:58)
>> From: Matthias Brugger <mbrugger@xxxxxxxx>
>>
>> Jasper send this series some month ago. As there was no reaction from
>> his side, I'll do a friendly take-over.
>> I tested the patches on my Helios X20 boards and they fix the issue.
>> I didn't add a Tested-by tag as I added my Signed-off-by.
>>
>> Changes since v1:
>> - add a fixes tag.
>>
>> ---
>>
>> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
>> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
>> system is booted without clk_ignore_unused.
>>
>> This patchset
>>
>> 1. Makes it possible to mark outputs of MUXes as critical by introducing
>>    a new macro, MUX_FLAGS,
>> 2. Makes it possible to mark gates as critical by adding flags to
>>    mtk_gate, and
>> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
>>    as critical.
>>
>> The addition of flags to mtk_gate also exists in the patch series "Add
>> basic and clock support for Mediatek MT8183 SoC" [1].  The type of
>> flags is unsigned int in that series, but the real type is unsigned
>> long, so my patch differs from that patch.
> 
> Will anyone from Mediatek review this? Why aren't the people who signed
> off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
> They no longer work there?
> 

My fault, I'll resend 3/3 with the comments you made. Added Kevin-CW now...