Re: [PATCH v2 1/3] dt-bindings: clk: meson: add ao controller clock inputs

[Jerome Brunet]

On Mon, 2018-12-03 at 14:18 +0100, Jerome Brunet wrote:
> Add the clock inputs of amlogic AO clock controller
> 
> Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxx>
> Signed-off-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> ---
>  .../devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt     | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt 
> b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
> index 3a880528030e..c480db8f4793 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt
> @@ -11,6 +11,11 @@ Required Properties:
>  	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
>  	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
>  	followed by the common "amlogic,meson-gx-aoclkc"
> +- clocks: list of clock phandle, one for each entry clock-names.
> +- clock-names: should contain the following:
> +  * "xtal"     : the platform xtal
> +  * "mpeg-clk" : the main clock controller mother clock (aka clk81)
> +  * "ext-32k"  : external 32kHz reference if any (optional)

While chip like the AXG have only 1 external 32k input, the gx family appears
to have 3 :( I missed that detail when preparing this patchset. Please hold
on, I'll send a v3

>  
>  - #clock-cells: should be 1.
>  
> @@ -40,8 +45,9 @@ ao_sysctrl: sys-ctrl@0 {
>  		compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-
> aoclkc";
>  		#clock-cells = <1>;
>  		#reset-cells = <1>;
> +		clocks = <&xtal>, <&clkc CLKID_CLK81>;
> +		clock-names = "xtal", "mpeg-clk";
>  	};
> -};
>  
>  Example: UART controller node that consumes the clock and reset generated
>    by the clock controller: