Re: [PATCH V6 4/9] clk: imx: add pfdv2 support

[Stephen Boyd]

Quoting A.s. Dong (2018-11-14 05:01:47)
> The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System
> Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP.
> 
> NOTE pfdv2 can only be operated when clk is gated.
> 
> Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: Anson Huang <Anson.Huang@xxxxxxx>
> Cc: Bai Ping <ping.bai@xxxxxxx>
> Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx>
> 
> ---

Applied to clk-next