Re: [PATCH 5/5] irqchip/irq-imx-gpcv2: Add support for i.MX8MQ

[Lucas Stach]

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Add code needed to support i.MX8MQ.
> 
> > Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> > Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
> > Cc: Marc Zyngier <marc.zyngier@xxxxxxx>
> Cc: cphealy@xxxxxxxxx
> Cc: l.stach@xxxxxxxxxxxxxx
> > Cc: Leonard Crestez <leonard.crestez@xxxxxxx>
> > Cc: "A.s. Dong" <aisheng.dong@xxxxxxx>
> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx>
> Cc: linux-imx@xxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> ---
> Âdrivers/irqchip/irq-imx-gpcv2.c | 31 +++++++++++++++++++++++++++++--
> Â1 file changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index c2b2b3128ddd..17a2dad2d4c2 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -17,6 +17,9 @@
> Â
> > Â#define GPC_IMR1_CORE0		0x30
> > Â#define GPC_IMR1_CORE1		0x40
> > +#define GPC_IMR1_CORE2		0x1c0
> > +#define GPC_IMR1_CORE3		0x1d0
> +
> Â
> Âstruct gpcv2_irqchip_data {
> > > Â	struct raw_spinlock	rlock;
> @@ -192,11 +195,19 @@ static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
> > > Â	.free		= irq_domain_free_irqs_common,
> Â};
> Â
> +static const struct of_device_id gpcv2_of_match[] = {
> > +	{ .compatible = "fsl,imx7d-gpc",ÂÂ.data = (const void *) 2 },
> > +	{ .compatible = "fsl,imx8mq-gpc", .data = (const void *) 4 },
> > +	{ /* END */ }
> +};
> +
> Âstatic int __init imx_gpcv2_irqchip_init(struct device_node *node,
> > Â			ÂÂÂÂÂÂÂstruct device_node *parent)
> Â{
> > Â	struct irq_domain *parent_domain, *domain;
> > Â	struct gpcv2_irqchip_data *cd;
> > +	const struct of_device_id *id;
> > +	unsigned long core_num;
> > Â	int i;
> Â
> > Â	if (!parent) {
> @@ -204,6 +215,14 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
> > Â		return -ENODEV;
> > Â	}
> Â
> > +	id = of_match_node(gpcv2_of_match, node);
> > +	if (!id) {
> > +		pr_err("%pOF: unknown compatibility string\n", node);
> > +		return -ENODEV;
> > +	}
> +
> > +	core_num = (unsigned long)id->data;
> +
> > Â	parent_domain = irq_find_host(parent);
> > Â	if (!parent_domain) {
> > Â		pr_err("%pOF: unable to get parent domain\n", node);
> @@ -236,8 +255,16 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node,
> Â
> > Â	/* Initially mask all interrupts */
> > Â	for (i = 0; i < IMR_NUM; i++) {
> > -		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
> > -		writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
> > +		void __iomem *reg = cd->gpc_base + i * 4;
> +
> > +		switch (core_num) {
> > +		case 4:
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE2);
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE3);
> > > +		case 2:	ÂÂÂÂÂÂ/* FALLTHROUGH */
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE0);
> > +			writel_relaxed(~0, reg + GPC_IMR1_CORE1);
> +		}

The writes being not being in linear descending core order does trigger
something in me, but obviously this doesn't has any effect on the code,
so:

Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>

> Â		cd->wakeup_sources[i] = ~0;
> > Â	}
> Â