diff --git a/arch/x86/entry/vdso/vsgx_enter_enclave.c b/arch/x86/entry/vdso/vsgx_enter_enclave.c
new file mode 100644
index 000000000000..896c2eb079bb
--- /dev/null
+++ b/arch/x86/entry/vdso/vsgx_enter_enclave.c
+enter_enclave:
+ asm volatile(
+ /*
+ * When an event occurs in an enclave, hardware first exits the
+ * enclave to the AEP, switching CPU context along the way, and
+ * *then* delivers the event as usual. As part of the context
+ * switching, registers are loaded with synthetic state (except
+ * BP and SP, which are saved/restored). The defined synthetic
+ * state loads registers so that simply executing ENCLU will do
+ * ERESUME, e.g. RAX=4, RBX=TCS and RCX=AEP after an AEE. So,
+ * we only need to load RAX, RBX and RCX for the initial entry.
+ * The AEP can point at that same ENCLU, fixup will jump us out
+ * if an exception was unhandled.
+ */
+ " lea 1f(%%rip), %%rcx\n"
+ "1: enclu\n"
+ "2:\n"
+
+ ".pushsection .fixup, \"ax\" \n"
+ "3: jmp 2b\n"
+ ".popsection\n"
+ _ASM_VDSO_EXTABLE_HANDLE(1b, 3b)
+
+ : "=a"(leaf), "=D" (rdi), "=S" (rsi), "=d" (rdx)
+ : "a" (leaf), "b" (tcs), "D" (priv)
+ : "cc", "memory",
+ "rcx", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
+ );
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