Re: [PATCH v2 0/3] ntb_hw_switchtec: Added support of >=4G memory windows
From: Jon Mason
Date: Wed Dec 12 2018 - 18:00:49 EST
On Thu, Dec 6, 2018 at 1:47 AM Wesley Sheng <wesley.sheng@xxxxxxxxxxxxx> wrote:
> Hi, Everyone,
> This patch series adds support of >=4G memory windows.
> Current Switchtec's BAR setup registers are limited to 32bits,
> corresponding to the maximum MW (memory window) size is <4G.
> Increase the MW sizes with the addition of the BAR Setup Extension
> Register for the upper 32bits of a 64bits MW size. This increases the MW
> range to between 4K and 2^63.
> Additionally, we've made the following changes:
> * debug print 64bit aligned crosslink BAR numbers
> * Fix the array size of NT req id mapping table
> Tested with ntb_test.sh successfully based on NTB fixes series from
> Logan Gunthorpe <logang@xxxxxxxxxxxx> at
> https://github.com/sbates130272/linux-p2pmem on branch of
So, you based your patches on a series of patches not in the
ntb/ntb-next branch? Please don't do this. I see nothing in these
patches which requires that series, which makes this even more
unnecessary. Since these are fairly trivial, I'm taking them and
pushing to the ntb-next branch to give these more time to be tested
(due to not being tested on the proper branch). I would really
appreciate you testing the ntb-next branch as a sanity check.
> Changed since v1:
> - Using upper_32_bits() and lower_32_bits() marcos makes it easier
> to read and avoids compiler warning on 32-bit arch
> - Reorder the patches to make the bug fixes first and add a "Fixes"
> line to the commit messages
> Paul Selles (2):
> ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers
> ntb_hw_switchtec: Added support of >=4G memory windows
> Wesley Sheng (1):
> ntb_hw_switchtec: NT req id mapping table register entry number should
> be 512
> drivers/ntb/hw/mscc/ntb_hw_switchtec.c | 11 ++++++++---
> include/linux/switchtec.h | 10 +++++++---
> 2 files changed, 15 insertions(+), 6 deletions(-)