RE: [v2] PCI: imx: make msi work without pcieportbus

[Richard Zhu]

Hi Lucas:

> -----Original Message-----
> From: Lucas Stach [mailto:l.stach@xxxxxxxxxxxxxx]
> Sent: 2018å12æ13æ 17:19
> To: Richard Zhu <hongxing.zhu@xxxxxxx>; bhelgaas@xxxxxxxxxx;
> lorenzo.pieralisi@xxxxxxx; andrew.smirnov@xxxxxxxxx
> Cc: linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [v2] PCI: imx: make msi work without pcieportbus
> 
> Hi Richard,
> 
> Am Donnerstag, den 13.12.2018, 08:02 +0000 schrieb Richard Zhu:
> > MSI_EN of iMX PCIe RC would be asserted when PCIEPORTBUS driver is
> > selected.
> > Thus, the MSI works fine on iMX PCIe before.
> > Assert it unconditionally when MSI is supported.
> > Otherwise, the MSI wouldn't be triggered although the EP is present
> > and the MSIs are assigned.
> 
> Thanks for digging into this issue. This seems like the right way forward.
> However, did you test this with devices using legacy IRQs?
> I.e. booting with "nomsi" on the kernel command line to see if legacy IRQs still
> work if this bit is set, or if we need to avoid setting this when the user
> explicitly requests to disable MSIs?
> 
> Regards,
> Lucas
> 
[Richard Zhu] Thanks for your review.
The Legacy INTx is broken.
The MSI_EN bit shouldn't be asserted when the user explicitly requests to disable MSIs.

BTW, regarding to Baruch's comments, it seems that all the (IS_ENABLED(CONFIG_PCI_MSI) check in
 the dwc host drivers are not required anymore, since the depends on PCI_MSI_IRQ_DOMAIN, right?


> > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > ---
> > Âdrivers/pci/controller/dwc/pci-imx6.c | 7 +++++++
> > Â1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 26087b3..d3e4296 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -74,6 +74,7 @@ struct imx6_pcie {
> > > Â#define PHY_PLL_LOCK_WAIT_USLEEP_MAX	200
> >
> > Â/* PCIe Root Complex registers (memory-mapped) */
> > > +#define PCI_MSI_CAP				0x50
> > > Â#define PCIE_RC_LCR				0x7c
> > > Â#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
> > > Â#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
> > @@ -926,6 +927,7 @@ static int imx6_pcie_probe(struct platform_device
> > *pdev)
> > > Â	struct resource *dbi_base;
> > > Â	struct device_node *node = dev->of_node;
> > > Â	int ret;
> > > +	u16 val;
> >
> > > Â	imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
> > > Â	if (!imx6_pcie)
> > @@ -1070,6 +1072,11 @@ static int imx6_pcie_probe(struct
> > platform_device *pdev)
> > > Â	ret = imx6_add_pcie_port(imx6_pcie, pdev);
> > > Â	if (ret < 0)
> > > Â		return ret;
> > > +	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > > +		val = dw_pcie_readw_dbi(pci, PCI_MSI_CAP +
> PCI_MSI_FLAGS);
> > > +		val |= PCI_MSI_FLAGS_ENABLE;
> > > +		dw_pcie_writew_dbi(pci, PCI_MSI_CAP + PCI_MSI_FLAGS, val);
> > > +	}
> >
> > > Â	return 0;
> > Â}