RE: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
From: Naga Sureshkumar Relli
Date: Tue Dec 18 2018 - 00:34:05 EST
> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@xxxxxxxxxxx]
> Sent: Monday, December 17, 2018 10:11 PM
> To: Naga Sureshkumar Relli <nagasure@xxxxxxxxxx>
> Cc: Boris Brezillon <boris.brezillon@xxxxxxxxxxx>; robh@xxxxxxxxxx; richard@xxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; marek.vasut@xxxxxxxxx; linux-mtd@xxxxxxxxxxxxxxxxxxx;
> nagasuresh12@xxxxxxxxx; Michal Simek <michals@xxxxxxxxxx>;
> computersforpeace@xxxxxxxxx; dwmw2@xxxxxxxxxxxxx
> Subject: Re: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for Arasan
> NAND Flash Controller
> Hi Naga,
> > Inserted biterror @ 48/7
> > Successfully corrected 25 bit errors per subpage Inserted biterror @
> > 50/7 ECC failure, invalid data despite read success
> > root@xilinx-zc1751-dc2-2018_1:~#
> > But even in this case also, driver is saying ECC failure but read success.
> > That means controller is able to detect errors on read page up to 24 bit only.
> > After that there is no way to say to the upper layers that the page is bad because of the
> limitation in the controller.
> This is more than a "limitation", the design is broken. I am not sure how to support such
> controller, and I am not sure if we even want to.
The number of errors that are correctable is limited by a parameter 't'(total number of errors),
If there is a condition that the number of errors greater than 't', then the controller won't be able to detect that.
I guess this concept is same for other controllers as well.
In Arasan it is limited to 24-bit.
Even, in case of Hamming, it is 1-bit error correction and 2-bit error detection.
What will happen if there are multiple errors(greater than 2-bit)?
Naga Sureshkumar Relli
> > Could you please suggest any alternative to report the errors in that case?
> Shall we support the controller without the hw ECC engine? Boris, any thoughts?