Re: [v4] PCI: imx: make msi work without CONFIG_PCIEPORTBUS=y

[Bjorn Helgaas]

[+cc Sven, Trent, et al from related report:
https://lore.kernel.org/linux-pci/20181218210444.5950-1-TheSven73@xxxxxxxxxxxxxx]

On Fri, Dec 14, 2018 at 06:44:15AM +0000, Richard Zhu wrote:
> Assertion of the MSI Enable bit of RC's MSI CAP is mandatory required to
> trigger MSI on i.MX6 PCIe.
> This bit would be asserted when CONFIG_PCIEPORTBUS=y.
> Thus, the MSI works fine on i.MX6 PCIe before the commit "f3fdfc4".
> 
> Assert it unconditionally when MSI is enabled.
> Otherwise, the MSI wouldn't be triggered although the EP is present and
> the MSIs are assigned.

OK, I think I finally understand most of what's going on.  Please
check the following possible changelog text:

  The MSI Enable bit in the MSI Capability (PCIe r4.0, sec 7.7.1.2)
  controls whether a Function can request service using MSI.

  i.MX6 Root Ports implement the MSI Capability and may use MSI to
  request service for events like PME, hotplug, AER, etc.  In
  addition, on i.MX6, the MSI Enable bit controls delivery of MSI
  interrupts from components below the Root Port.

  Prior to f3fdfc4ac3a2 ("PCI: Remove host driver Kconfig selection of
  CONFIG_PCIEPORTBUS"), enabling CONFIG_PCI_IMX6 automatically also
  enabled CONFIG_PCIEPORTBUS, and when portdrv claimed the Root Ports,
  it set the MSI Enable bit so it could use PME, hotplug, AER, etc.
  As a side effect, that also enabled delivery of MSI interrupts from
  downstream components.

  After f3fdfc4ac3a2, the imx6q-pcie driver can operate without
  portdrv, but that means imx6q-pcie must set the MSI Enable bit
  itself if downstream components use MSI.

  Fixes: f3fdfc4ac3a2 ("PCI: Remove host driver Kconfig selection of CONFIG_PCIEPORTBUS")

I still don't understand exactly *how* MSI Enable affects MSI from
downstream components, since the downstream component just does a DMA
write, and the Root Port can't tell whether the write is to memory or
interrupt controller unless the Root Port knows where the MSI targets
are, e.g., if the interrupt controller is actually part of the RC.

Bjorn

> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> Reviewed-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> ---
> Changes v1 -> v2:
> * Assert the MSI_EN unconditionally when MSI is supported.
> Changes v2 -> v3:
> * Remove the IS_ENABLED(CONFIG_PCI_MSI) since the driver depends on
> PCI_MSI_IRQ_DOMAIN
> * Extended with a check for pci_msi_enabled() to see if the user
> explicitly want legacy IRQs
> Changes v3 -> v4:
> * Refer to Bjorn's comments, refine the subject and commit log and change
> the PCI_MSI_CAP to PCIE_RC_IMX6_MSI_CAP.
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 26087b3..639bb27 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -74,6 +74,7 @@ struct imx6_pcie {
>  #define PHY_PLL_LOCK_WAIT_USLEEP_MAX	200
>  
>  /* PCIe Root Complex registers (memory-mapped) */
> +#define PCIE_RC_IMX6_MSI_CAP			0x50
>  #define PCIE_RC_LCR				0x7c
>  #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	0x1
>  #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	0x2
> @@ -926,6 +927,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>  	struct resource *dbi_base;
>  	struct device_node *node = dev->of_node;
>  	int ret;
> +	u16 val;
>  
>  	imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
>  	if (!imx6_pcie)
> @@ -1071,6 +1073,14 @@ static int imx6_pcie_probe(struct platform_device *pdev)
>  	if (ret < 0)
>  		return ret;
>  
> +	if (pci_msi_enabled()) {
> +		val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
> +				PCI_MSI_FLAGS);
> +		val |= PCI_MSI_FLAGS_ENABLE;
> +		dw_pcie_writew_dbi(pci, PCIE_RC_MSI_IMX6_CAP +
> +				PCI_MSI_FLAGS, val);
> +	}
> +
>  	return 0;
>  }
>  
> -- 
> 2.7.4
> 
> 
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