Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency

[Daniel Lezcano]

On 04/01/2019 01:36, Palmer Dabbelt wrote:
> On Fri, 14 Dec 2018 01:17:24 PST (-0800), daniel.lezcano@xxxxxxxxxx wrote:
>> On 14/12/2018 00:14, Atish Patra wrote:
>>> From: Palmer Dabbelt <palmer@xxxxxxxxxx>
>>>
>>> In RISC-V systems, timebase-frequency is per cpu instead of one
>>> instance for entire SOC as there is a individual timer per each CPU.
>>> Fix the DT binding accordingly.
>>
>> Why not use a fixed-clock instead of this timebase property which forces
>> to declare a global variable to be exported from arch/riscv to
>> drivers/clocksource ?
> 
> That makes sense to me. I've always disliked this global variable and a
> big part of why my original version got delayed forever is that I'd
> hoped to get rid of it.
> 
> Given that this is all a mess anyway I'm OK breaking backwards
> compatibility here.
> 
> Is there an example of how to do this?


Can you give some hardware details? Is the timebase frequency constant?
If it is the case, a fixed-clock shared for each cpu can be used, no?

    myclock: myclock {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency  = <1000000>;
        clock-output-names = "mytimer";
    };

Alternatively, may be different output can be specified with the clock,
one for each CPUs.

Or if the timebase frequency is resulting from a clock divisor, it can
be defined as:

        clock {
                compatible = "fixed-factor-clock";
                clocks = <&parentclk>;
                #clock-cells = <0>;
                clock-div = <2>;
                clock-mult = <1>;
        };

hardware details can help to narrow down the right description.


>> In addition, please add the 'Fixes' tag
>>
>>> Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxx>
>>> Signed-off-by: Christoph Hellwig <hch@xxxxxx>
>>> [Atish: Update the commit text]
>>> Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
>>> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
>>> ---
>>> ÂDocumentation/devicetree/bindings/riscv/cpus.txt | 4 +++-
>>> Â1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt
>>> b/Documentation/devicetree/bindings/riscv/cpus.txt
>>> index adf7b7af..b0b038d6 100644
>>> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
>>> @@ -93,9 +93,9 @@ Linux is allowed to run on.
>>> ÂÂÂÂÂÂÂÂ cpus {
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ #address-cells = <1>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ #size-cells = <0>;
>>> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timebase-frequency = <1000000>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cpu@0 {
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ clock-frequency = <1600000000>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timebase-frequency = <1000000>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ compatible = "sifive,rocket0", "riscv";
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ device_type = "cpu";
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ i-cache-block-size = <64>;
>>> @@ -113,6 +113,7 @@ Linux is allowed to run on.
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ };
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cpu@1 {
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ clock-frequency = <1600000000>;
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timebase-frequency = <1000000>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ compatible = "sifive,rocket0", "riscv";
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ d-cache-block-size = <64>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ d-cache-sets = <64>;
>>> @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart
>>> ÂThis device tree matches the Spike ISA golden model as run with
>>> `spike -p1`.
>>>
>>> ÂÂÂÂÂÂÂÂ cpus {
>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timebase-frequency = <1000000>;
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cpu@0 {
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ device_type = "cpu";
>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ reg = <0x00000000>;


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