[PATCH V5 4/4] perf/x86/intel: Add counter freezing quirk for Goldmont

[kan . liang]

From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>

A ucode patch is also needed for Goldmont while counter freezing feature
is enabled. Otherwise, there will be some issues, e.g. PMI lost.

Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
---

- New patch, merged from https://lkml.org/lkml/2018/10/3/25

 arch/x86/events/intel/core.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index e94731e..99be2d5 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3939,6 +3939,10 @@ static __init void intel_nehalem_quirk(void)
 }
 
 static const struct x86_cpu_check counter_freezing_ucodes[] = {
+	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT,		2, 0x0000000e),
+	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT,		9, 0x0000002e),
+	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT,		10, 0x00000008),
+	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT_X,		1, 0x00000028),
 	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT_PLUS,	1, 0x00000028),
 	INTEL_CHECK_UCODE(INTEL_FAM6_ATOM_GOLDMONT_PLUS,	8, 0x00000006),
 	{}
@@ -4310,6 +4314,7 @@ __init int intel_pmu_init(void)
 
 	case INTEL_FAM6_ATOM_GOLDMONT:
 	case INTEL_FAM6_ATOM_GOLDMONT_X:
+		x86_add_quirk(intel_counter_freezing_quirk);
 		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
-- 
2.7.4