Re: [PATCH V7 2/2] drm/panel: Add Sitronix ST7701 panel driver

[Jagan Teki]

On Sat, Jan 12, 2019 at 5:31 PM Sam Ravnborg <sam@xxxxxxxxxxxx> wrote:
>
> > >
> > > > > > +
> > > > > > +     msleep(st7701->sleep_delay);
> > > > > > +
> > > > > > +     gpiod_set_value(st7701->reset, 0);
> > > > > > +
> > > > > > +     gpiod_set_value(st7701->reset, 1);
> > > > > > +
> > > > > > +     gpiod_set_value(st7701->reset, 0);
> > > > > No timing constrains here? In prepare there are sleeps intermixed.
> > > >
> > > > Delay while doing unprare is not needed I suppose.
> > >
> > > If the purpose is alone to reset the display then a single write '0'
> > > should do it I think
> >
> > I even tried this just set 0, since prepare is doing a sequence, it
> > good behavior to do the reverse during handoff. ie reason I just
> > initiated this sequence.
> >
> > > And there is a requirement that it must be low for a minimum of 10 us
> > > which would be good to have here.
> >
> > Sorry, I didn't get this requirement what is this for?
> The st7701 will ignore reset pulse shorter than 10 us - see Trw in
> table 9 reset timing (page 54).
>
> But as we just assert reset (set it to 0), this timing constraint can be ignored.

But we unaware of reset pulse duration right? it's the hardware that
bring the reset assert if we set the line 0. am I correct or do we
need to explicitly wait 10us after reset initiated?
there is family of chip Sitronix st7789v which don't taking care of
this sequence (I don't know why?) in
drivers/gpu/drm/panel/panel-sitronix-st7789v.c with Page 48 of
datasheet[2]

[2] https://www.newhavendisplay.com/appnotes/datasheets/LCDs/ST7789V.pdf