RE: [PATCH V8 1/3] dt-bindings: mmc: tegra: Add supports-cqe property

[Sowjanya Komatineni]

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>> Add supports-cqe optional property for Tegra SDMMC.
>> 
>> Tegra186 and Tegra194 supports HW Command queue only on SDMMC4 
>> controller. This property is used to identify command queue support 
>> controller in the tegra sdhci driver.
>> 
>> Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx>
>> ---
>>  Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 4 
>> ++++
>>  1 file changed, 4 insertions(+)
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt 
>> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> index 32b4b4e41923..fb14c2c8d7ee 100644
>> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> @@ -72,6 +72,10 @@ Optional properties for Tegra210 and Tegra186:
>>  - nvidia,default-trim : Specify the default outbound clock trimmer
>>    value.
>>  - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
>> +- supports-cqe : The presence of this property indicates that the
>> +  corresponding controller supports HW command queue feature.
>> +  Tegra186 and Tegra194 has 4 SDMMC Controllers and only SDMMC4
>> +  controller supports HW Command Queue with eMMC device.
>
>Don't SDHCI capability bits do this? If not, this should probably be common.
>
>Rob

Tegra has 4 SDMMC controllers and HW Command queue is supported only on SDMMC4.
There is no bit field specific in SDMMC4 alone to indicate this. So added supports-cqe to
identifying this thru Device tree.

Thanks
Sowjanya