Re: [PATCH v2 1/7] KVM:VMX: Define CET VMCS fields and bits

[Yang Weijiang]

On Fri, Jan 25, 2019 at 07:02:37PM +0100, Paolo Bonzini wrote:
> On 22/01/19 21:59, Yang Weijiang wrote:
> > On processors that support CET, VMX saves/restores
> > the states of IA32_S_CET, SSP and IA32_INTERRUPT_SSP_TABLE_ADDR MSR
> > to the VMCS area for Guest/Host unconditionally.
> > 
> > If VM_EXIT_LOAD_HOST_CET_STATE = 1, the host CET MSRs are
> > restored from VMCS host-state area at VM exit as follows:
> > 
> > - HOST_IA32_S_CET: Host supervisor mode IA32_S_CET MSR is loaded
> >                    from this field.
> > 
> > - HOST_SSP : Host SSP is loaded from this field.
> > 
> > - HOST_INTR_SSP_TABLE_ADDR : Host IA32_INTERRUPT_SSP_TABLE_ADDR
> >                              MSR is loaded from this field.
> > 
> > If VM_ENTRY_LOAD_GUEST_CET_STATE = 1, the guest CET MSRs are loaded
> > from VMCS guest-state area at VM entry as follows:
> > 
> > - GUEST_IA32_S_CET : Guest supervisor mode IA32_S_CET MSR is loaded
> >                      from this field.
> > 
> > - GUEST_SSP : Guest SSP is loaded from this field.
> > 
> > - GUEST_INTR_SSP_TABL_ADDR : Guest IA32_INTERRUPT_SSP_TABLE_ADDR
> >                              MSR is loaded from this field.
>
Thanks for review.

> There is no code in this series to pass these fields to and from
> userspace, and also to save/restore U_CET, INT_SSP_TAB, PL0_SSP and
> PL3_SSP across context switches.
> 
The kernel consumes these MSRs, please see kernel CET patch:
https://lkml.org/lkml/fancy/2018/11/20/225

> In addition, PL1_SSP and PL2_SSP should be supported even if the guest
> doesn't use them.  It makes sense to avoid intercepting them, but they
> should still be supported and switched (possibly only if nonzero).
> 
> Am I missing something, for example a dependency on host CET support?
> If not, how was this series tested?
> 
The guest CET feature is tested with kernel CET patches on internal
virtual platform.

> Paolo