Re: [PATCH V5 2/7] clocksource: tegra: add Tegra210 timer support

From: Dmitry Osipenko
Date: Fri Feb 01 2019 - 10:13:25 EST

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01.02.2019 17:13, Joseph Lo ÐÐÑÐÑ:
> On 2/1/19 9:54 PM, Jon Hunter wrote:
>>
>> On 01/02/2019 13:11, Dmitry Osipenko wrote:
>>> 01.02.2019 16:06, Dmitry Osipenko ÐÐÑÐÑ:
>>>> 01.02.2019 6:36, Joseph Lo ÐÐÑÐÑ:
>>>>> Add support for the Tegra210 timer that runs at oscillator clock
>>>>> (TMR10-TMR13). We need these timers to work as clock event device and to
>>>>> replace the ARMv8 architected timer due to it can't survive across the
>>>>> power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up
>>>>> source when CPU suspends in power down state.
>>>>>
>>>>> Also convert the original driver to use timer-of API.
>>>>>
>>>>> Cc: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
>>>>> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
>>>>> Cc: linux-kernel@xxxxxxxxxxxxxxx
>>>>> Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
>>>>> Acked-by: Thierry Reding <treding@xxxxxxxxxx>
>>>>> ---
>>>>> v5:
>>>>> Â * add ack tag from Thierry
>>>>> v4:
>>>>> Â * merge timer-tegra210.c in previous version into timer-tegra20.c
>>>>> v3:
>>>>> Â * use timer-of API
>>>>> v2:
>>>>> Â * add error clean-up code
>>>>> ---
>>>>> Â drivers/clocksource/KconfigÂÂÂÂÂÂÂÂ |ÂÂ 2 +-
>>>>> Â drivers/clocksource/timer-tegra20.c | 369 ++++++++++++++++++++--------
>>>>> Â include/linux/cpuhotplug.hÂÂÂÂÂÂÂÂÂ |ÂÂ 1 +
>>>>> Â 3 files changed, 272 insertions(+), 100 deletions(-)
>>>>>
>>>>> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
>>>>> index a9e26f6a81a1..6af78534a285 100644
>>>>> --- a/drivers/clocksource/Kconfig
>>>>> +++ b/drivers/clocksource/Kconfig
>>>>> @@ -131,7 +131,7 @@ config SUN5I_HSTIMER
>>>>> Â config TEGRA_TIMER
>>>>> ÂÂÂÂÂ bool "Tegra timer driver" if COMPILE_TEST
>>>>> ÂÂÂÂÂ select CLKSRC_MMIO
>>>>> -ÂÂÂ depends on ARM
>>>>> +ÂÂÂ select TIMER_OF
>>>>> ÂÂÂÂÂ help
>>>>> ÂÂÂÂÂÂÂ Enables support for the Tegra driver.
>>>>> Â diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c
>>>>> index 4293943f4e2b..96a809341c9b 100644
>>>>> --- a/drivers/clocksource/timer-tegra20.c
>>>>> +++ b/drivers/clocksource/timer-tegra20.c
>>>>> @@ -15,21 +15,24 @@
>>>>> ÂÂ *
>>>>> ÂÂ */
>>>>> Â -#include <linux/init.h>
>>>>> +#include <linux/clk.h>
>>>>> +#include <linux/clockchips.h>
>>>>> +#include <linux/cpu.h>
>>>>> +#include <linux/cpumask.h>
>>>>> +#include <linux/delay.h>
>>>>> Â #include <linux/err.h>
>>>>> -#include <linux/time.h>
>>>>> Â #include <linux/interrupt.h>
>>>>> -#include <linux/irq.h>
>>>>> -#include <linux/clockchips.h>
>>>>> -#include <linux/clocksource.h>
>>>>> -#include <linux/clk.h>
>>>>> -#include <linux/io.h>
>>>>> Â #include <linux/of_address.h>
>>>>> Â #include <linux/of_irq.h>
>>>>> -#include <linux/sched_clock.h>
>>>>> -#include <linux/delay.h>
>>>>> +#include <linux/percpu.h>
>>>>> +#include <linux/syscore_ops.h>
>>>>> +#include <linux/time.h>
>>>>> +
>>>>> +#include "timer-of.h"
>>>>> Â +#ifdef CONFIG_ARM
>>>>> Â #include <asm/mach/time.h>
>>>>> +#endif
>>>>> Â Â #define RTC_SECONDSÂÂÂÂÂÂÂÂÂÂÂ 0x08
>>>>> Â #define RTC_SHADOW_SECONDSÂÂÂÂ 0x0c
>>>>> @@ -43,70 +46,147 @@
>>>>> Â #define TIMER2_BASE 0x8
>>>>> Â #define TIMER3_BASE 0x50
>>>>> Â #define TIMER4_BASE 0x58
>>>>> -
>>>>> -#define TIMER_PTV 0x0
>>>>> -#define TIMER_PCR 0x4
>>>>> -
>>>>> +#define TIMER10_BASE 0x90
>>>>> +
>>>>> +#define TIMER_PTVÂÂÂÂÂÂÂ 0x0
>>>>> +#define TIMER_PTV_ENÂÂÂÂÂÂÂ BIT(31)
>>>>> +#define TIMER_PTV_PERÂÂÂÂÂÂÂ BIT(30)
>>>>> +#define TIMER_PCRÂÂÂÂÂÂÂ 0x4
>>>>> +#define TIMER_PCR_INTR_CLRÂÂÂ BIT(30)
>>>>> +
>>>>> +#ifdef CONFIG_ARM
>>>>> +#define TIMER_BASE TIMER3_BASE
>>>>> +#else
>>>>> +#define TIMER_BASE TIMER10_BASE
>>>>> +#endif
>>>>> +#define TIMER10_IRQ_IDXÂÂÂÂÂÂÂ 10
>>>>> +#define TIMER_FOR_CPU(cpu) (TIMER_BASE + (cpu) * 8)
>>>>> +#define IRQ_IDX_FOR_CPU(cpu)ÂÂÂ (TIMER10_IRQ_IDX + cpu)
>>>>> +
>>>>> +static u32 usec_config;
>>>>> Â static void __iomem *timer_reg_base;
>>>>> +#ifdef CONFIG_ARM
>>>>> Â static void __iomem *rtc_base;
>>>>> -
>>>>> Â static struct timespec64 persistent_ts;
>>>>> Â static u64 persistent_ms, last_persistent_ms;
>>>>> -
>>>>> Â static struct delay_timer tegra_delay_timer;
>>>>> -
>>>>> -#define timer_writel(value, reg) \
>>>>> -ÂÂÂ writel_relaxed(value, timer_reg_base + (reg))
>>>>> -#define timer_readl(reg) \
>>>>> -ÂÂÂ readl_relaxed(timer_reg_base + (reg))
>>>>> +#endif
>>>>> Â Â static int tegra_timer_set_next_event(unsigned long cycles,
>>>>> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct clock_event_device *evt)
>>>>> Â {
>>>>> -ÂÂÂ u32 reg;
>>>>> +ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>>> Â -ÂÂÂ reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
>>>>> -ÂÂÂ timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>>>> +ÂÂÂ writel(TIMER_PTV_EN |
>>>>> +ÂÂÂÂÂÂÂÂÂÂ ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
>>>>> +ÂÂÂÂÂÂÂÂÂÂ reg_base + TIMER_PTV);
>>>>> Â ÂÂÂÂÂ return 0;
>>>>> Â }
>>>>> Â -static inline void timer_shutdown(struct clock_event_device *evt)
>>>>> +static int tegra_timer_shutdown(struct clock_event_device *evt)
>>>>> Â {
>>>>> -ÂÂÂ timer_writel(0, TIMER3_BASE + TIMER_PTV);
>>>>> +ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>>> +
>>>>> +ÂÂÂ writel(0, reg_base + TIMER_PTV);
>>>>> +
>>>>> +ÂÂÂ return 0;
>>>>> Â }
>>>>> Â -static int tegra_timer_shutdown(struct clock_event_device *evt)
>>>>> +static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>>> Â {
>>>>> -ÂÂÂ timer_shutdown(evt);
>>>>> +ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>>> +
>>>>> +ÂÂÂ writel(TIMER_PTV_EN | TIMER_PTV_PER |
>>>>> +ÂÂÂÂÂÂÂÂÂÂ ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
>>>>> +ÂÂÂÂÂÂÂÂÂÂ reg_base + TIMER_PTV);
>>>>> +
>>>>> ÂÂÂÂÂ return 0;
>>>>> Â }
>>>>> Â -static int tegra_timer_set_periodic(struct clock_event_device *evt)
>>>>> +static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
>>>>> Â {
>>>>> -ÂÂÂ u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
>>>>> +ÂÂÂ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>>>>> +ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
>>>>> +
>>>>> +ÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>>>> +ÂÂÂ evt->event_handler(evt);
>>>>> +
>>>>> +ÂÂÂ return IRQ_HANDLED;
>>>>> +}
>>>>> +
>>>>> +#ifdef CONFIG_ARM64
>>>>> +static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
>>>>> +ÂÂÂ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
>>>>> +
>>>>> +ÂÂÂ .clkevt = {
>>>>> +ÂÂÂÂÂÂÂ .name = "tegra_timer",
>>>>> +ÂÂÂÂÂÂÂ .rating = 460,
>>>>> +ÂÂÂÂÂÂÂ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
>>>>> +ÂÂÂÂÂÂÂ .set_next_event = tegra_timer_set_next_event,
>>>>> +ÂÂÂÂÂÂÂ .set_state_shutdown = tegra_timer_shutdown,
>>>>> +ÂÂÂÂÂÂÂ .set_state_periodic = tegra_timer_set_periodic,
>>>>> +ÂÂÂÂÂÂÂ .set_state_oneshot = tegra_timer_shutdown,
>>>>> +ÂÂÂÂÂÂÂ .tick_resume = tegra_timer_shutdown,
>>>>> +ÂÂÂ },
>>>>> +};
>>>>> +
>>>>> +static int tegra_timer_setup(unsigned int cpu)
>>>>> +{
>>>>> +ÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>>>> +
>>>>> +ÂÂÂ irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
>>>>> +ÂÂÂ enable_irq(to->clkevt.irq);
>>>>> +
>>>>> +ÂÂÂ clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1, /* min */
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x1fffffff); /* 29 bits */
>>>>> Â -ÂÂÂ timer_shutdown(evt);
>>>>> -ÂÂÂ timer_writel(reg, TIMER3_BASE + TIMER_PTV);
>>>>> ÂÂÂÂÂ return 0;
>>>>> Â }
>>>>> Â -static struct clock_event_device tegra_clockevent = {
>>>>> -ÂÂÂ .nameÂÂÂÂÂÂÂÂÂÂÂ = "timer0",
>>>>> -ÂÂÂ .ratingÂÂÂÂÂÂÂÂÂÂÂ = 300,
>>>>> -ÂÂÂ .featuresÂÂÂÂÂÂÂ = CLOCK_EVT_FEAT_ONESHOT |
>>>>> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_PERIODIC |
>>>>> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_DYNIRQ,
>>>>> -ÂÂÂ .set_next_eventÂÂÂÂÂÂÂ = tegra_timer_set_next_event,
>>>>> -ÂÂÂ .set_state_shutdownÂÂÂ = tegra_timer_shutdown,
>>>>> -ÂÂÂ .set_state_periodicÂÂÂ = tegra_timer_set_periodic,
>>>>> -ÂÂÂ .set_state_oneshotÂÂÂ = tegra_timer_shutdown,
>>>>> -ÂÂÂ .tick_resumeÂÂÂÂÂÂÂ = tegra_timer_shutdown,
>>>>> +static int tegra_timer_stop(unsigned int cpu)
>>>>> +{
>>>>> +ÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>>>> +
>>>>> +ÂÂÂ to->clkevt.set_state_shutdown(&to->clkevt);
>>>>> +ÂÂÂ disable_irq_nosync(to->clkevt.irq);
>>>>> +
>>>>> +ÂÂÂ return 0;
>>>>> +}
>>>>> +#else /* CONFIG_ARM */
>>>>> +static struct timer_of tegra_to = {
>>>>> +ÂÂÂ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
>>>>> +
>>>>> +ÂÂÂ .clkevt = {
>>>>> +ÂÂÂÂÂÂÂ .name = "tegra_timer",
>>>>> +ÂÂÂÂÂÂÂ .ratingÂÂÂ = 300,
>>>>> +ÂÂÂÂÂÂÂ .features = CLOCK_EVT_FEAT_ONESHOT |
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_PERIODIC |
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_DYNIRQ,
>>>>> +ÂÂÂÂÂÂÂ .set_next_eventÂÂÂ = tegra_timer_set_next_event,
>>>>> +ÂÂÂÂÂÂÂ .set_state_shutdown = tegra_timer_shutdown,
>>>>> +ÂÂÂÂÂÂÂ .set_state_periodic = tegra_timer_set_periodic,
>>>>> +ÂÂÂÂÂÂÂ .set_state_oneshot = tegra_timer_shutdown,
>>>>> +ÂÂÂÂÂÂÂ .tick_resume = tegra_timer_shutdown,
>>>>> +ÂÂÂÂÂÂÂ .cpumask = cpu_possible_mask,
>>>>> +ÂÂÂ },
>>>>> +
>>>>> +ÂÂÂ .of_irq = {
>>>>> +ÂÂÂÂÂÂÂ .index = 2,
>>>>> +ÂÂÂÂÂÂÂ .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>>>> +ÂÂÂÂÂÂÂ .handler = tegra_timer_isr,
>>>>> +ÂÂÂ },
>>>>> Â };
>>>>> Â Â static u64 notrace tegra_read_sched_clock(void)
>>>>> Â {
>>>>> -ÂÂÂ return timer_readl(TIMERUS_CNTR_1US);
>>>>> +ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>>>> +}
>>>>> +
>>>>> +static unsigned long tegra_delay_timer_read_counter_long(void)
>>>>> +{
>>>>> +ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>>>> Â }
>>>>> Â Â /*
>>>>> @@ -143,98 +223,188 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts)
>>>>> ÂÂÂÂÂ timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
>>>>> ÂÂÂÂÂ *ts = persistent_ts;
>>>>> Â }
>>>>> +#endif
>>>>> Â -static unsigned long tegra_delay_timer_read_counter_long(void)
>>>>> +static int tegra_timer_suspend(void)
>>>>> Â {
>>>>> -ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
>>>>> +#ifdef CONFIG_ARM64
>>>>> +ÂÂÂ int cpu;
>>>>> +
>>>>> +ÂÂÂ for_each_possible_cpu(cpu) {
>>>>> +ÂÂÂÂÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
>>>>> +ÂÂÂÂÂÂÂ void __iomem *reg_base = timer_of_base(to);
>>>>> +
>>>>> +ÂÂÂÂÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>>>> +ÂÂÂ }
>>>>> +#else
>>>>> +ÂÂÂ void __iomem *reg_base = timer_of_base(&tegra_to);
>>>>> +
>>>>> +ÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
>>>>> +#endif
>>>>> +
>>>>> +ÂÂÂ return 0;
>>>>> Â }
>>>>> Â -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
>>>>> +static void tegra_timer_resume(void)
>>>>> Â {
>>>>> -ÂÂÂ struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>>>>> -ÂÂÂ timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
>>>>> -ÂÂÂ evt->event_handler(evt);
>>>>> -ÂÂÂ return IRQ_HANDLED;
>>>>> +ÂÂÂ writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
>>>>> Â }
>>>>> Â -static struct irqaction tegra_timer_irq = {
>>>>> -ÂÂÂ .nameÂÂÂÂÂÂÂ = "timer0",
>>>>> -ÂÂÂ .flagsÂÂÂÂÂÂÂ = IRQF_TIMER | IRQF_TRIGGER_HIGH,
>>>>> -ÂÂÂ .handlerÂÂÂ = tegra_timer_interrupt,
>>>>> -ÂÂÂ .dev_idÂÂÂÂÂÂÂ = &tegra_clockevent,
>>>>> +static struct syscore_ops tegra_timer_syscore_ops = {
>>>>> +ÂÂÂ .suspend = tegra_timer_suspend,
>>>>> +ÂÂÂ .resume = tegra_timer_resume,
>>>>> Â };
>>>>> Â -static int __init tegra20_init_timer(struct device_node *np)
>>>>> +static int tegra_timer_init(struct device_node *np, struct timer_of *to)
>>>>> Â {
>>>>> -ÂÂÂ struct clk *clk;
>>>>> -ÂÂÂ unsigned long rate;
>>>>> -ÂÂÂ int ret;
>>>>> +ÂÂÂ int ret = 0;
>>>>> Â -ÂÂÂ timer_reg_base = of_iomap(np, 0);
>>>>> -ÂÂÂ if (!timer_reg_base) {
>>>>> -ÂÂÂÂÂÂÂ pr_err("Can't map timer registers\n");
>>>>> -ÂÂÂÂÂÂÂ return -ENXIO;
>>>>> -ÂÂÂ }
>>>>> +ÂÂÂ ret = timer_of_init(np, to);
>>>>> +ÂÂÂ if (ret < 0)
>>>>> +ÂÂÂÂÂÂÂ goto out;
>>>>> Â -ÂÂÂ tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
>>>>> -ÂÂÂ if (tegra_timer_irq.irq <= 0) {
>>>>> -ÂÂÂÂÂÂÂ pr_err("Failed to map timer IRQ\n");
>>>>> -ÂÂÂÂÂÂÂ return -EINVAL;
>>>>> -ÂÂÂ }
>>>>> +ÂÂÂ timer_reg_base = timer_of_base(to);
>>>>> Â -ÂÂÂ clk = of_clk_get(np, 0);
>>>>> -ÂÂÂ if (IS_ERR(clk)) {
>>>>> -ÂÂÂÂÂÂÂ pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
>>>>> -ÂÂÂÂÂÂÂ rate = 12000000;
>>>>> -ÂÂÂ } else {
>>>>> -ÂÂÂÂÂÂÂ clk_prepare_enable(clk);
>>>>> -ÂÂÂÂÂÂÂ rate = clk_get_rate(clk);
>>>>> -ÂÂÂ }
>>>>> -
>>>>> -ÂÂÂ switch (rate) {
>>>>> +ÂÂÂ /*
>>>>> +ÂÂÂÂ * Configure microsecond timers to have 1MHz clock
>>>>> +ÂÂÂÂ * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
>>>>> +ÂÂÂÂ * Uses n+1 scheme
>>>>> +ÂÂÂÂ */
>>>>> +ÂÂÂ switch (timer_of_rate(to)) {
>>>>> ÂÂÂÂÂ case 12000000:
>>>>> -ÂÂÂÂÂÂÂ timer_writel(0x000b, TIMERUS_USEC_CFG);
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x000b; /* (11+1)/(0+1) */
>>>>> +ÂÂÂÂÂÂÂ break;
>>>>> +ÂÂÂ case 12800000:
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x043f; /* (63+1)/(4+1) */
>>>>> ÂÂÂÂÂÂÂÂÂ break;
>>>>> ÂÂÂÂÂ case 13000000:
>>>>> -ÂÂÂÂÂÂÂ timer_writel(0x000c, TIMERUS_USEC_CFG);
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x000c; /* (12+1)/(0+1) */
>>>>> +ÂÂÂÂÂÂÂ break;
>>>>> +ÂÂÂ case 16800000:
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x0453; /* (83+1)/(4+1) */
>>>>> ÂÂÂÂÂÂÂÂÂ break;
>>>>> ÂÂÂÂÂ case 19200000:
>>>>> -ÂÂÂÂÂÂÂ timer_writel(0x045f, TIMERUS_USEC_CFG);
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x045f; /* (95+1)/(4+1) */
>>>>> ÂÂÂÂÂÂÂÂÂ break;
>>>>> ÂÂÂÂÂ case 26000000:
>>>>> -ÂÂÂÂÂÂÂ timer_writel(0x0019, TIMERUS_USEC_CFG);
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x0019; /* (25+1)/(0+1) */
>>>>> +ÂÂÂÂÂÂÂ break;
>>>>> +ÂÂÂ case 38400000:
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x04bf; /* (191+1)/(4+1) */
>>>>> +ÂÂÂÂÂÂÂ break;
>>>>> +ÂÂÂ case 48000000:
>>>>> +ÂÂÂÂÂÂÂ usec_config = 0x002f; /* (47+1)/(0+1) */
>>>>> ÂÂÂÂÂÂÂÂÂ break;
>>>>> ÂÂÂÂÂ default:
>>>>> -ÂÂÂÂÂÂÂ WARN(1, "Unknown clock rate");
>>>>> +ÂÂÂÂÂÂÂ ret = -EINVAL;
>>>>> +ÂÂÂÂÂÂÂ goto out;
>>>>> +ÂÂÂ }
>>>>> +
>>>>> +ÂÂÂ writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
>>>>> +
>>>>> +ÂÂÂ register_syscore_ops(&tegra_timer_syscore_ops);
>>>>> +out:
>>>>> +ÂÂÂ return ret;
>>>>> +}
>>>>> +
>>>>> +#ifdef CONFIG_ARM64
>>>>> +static int __init tegra210_timer_init(struct device_node *np)
>>>>> +{
>>>>> +ÂÂÂ int cpu, ret = 0;
>>>>> +ÂÂÂ struct timer_of *to;
>>>>> +
>>>>> +ÂÂÂ to = this_cpu_ptr(&tegra_to);
>>>>> +ÂÂÂ ret = tegra_timer_init(np, to);
>>>>> +ÂÂÂ if (ret < 0)
>>>>> +ÂÂÂÂÂÂÂ goto out;
>>>>> +
>>>>> +ÂÂÂ for_each_possible_cpu(cpu) {
>>>>> +ÂÂÂÂÂÂÂ struct timer_of *cpu_to;
>>>>> +
>>>>> +ÂÂÂÂÂÂÂ cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>>>> +ÂÂÂÂÂÂÂ cpu_to->of_base.base = timer_reg_base + TIMER_FOR_CPU(cpu);
>>>>> +ÂÂÂÂÂÂÂ cpu_to->of_clk.rate = timer_of_rate(to);
>>>>> +ÂÂÂÂÂÂÂ cpu_to->clkevt.cpumask = cpumask_of(cpu);
>>>>> +
>>>>> +ÂÂÂÂÂÂÂ cpu_to->clkevt.irq =
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
>>>>> +ÂÂÂÂÂÂÂ if (!cpu_to->clkevt.irq) {
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ pr_err("%s: can't map IRQ for CPU%d\n",
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ __func__, cpu);
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ ret = -EINVAL;
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ goto out;
>>>>> +ÂÂÂÂÂÂÂ }
>>>>> +
>>>>> +ÂÂÂÂÂÂÂ irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
>>>>> +ÂÂÂÂÂÂÂ ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ IRQF_TIMER | IRQF_NOBALANCING,
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cpu_to->clkevt.name, &cpu_to->clkevt);
>>>>> +ÂÂÂÂÂÂÂ if (ret) {
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ pr_err("%s: cannot setup irq %d for CPU%d\n",
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ __func__, cpu_to->clkevt.irq, cpu);
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ ret = -EINVAL;
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ goto out_irq;
>>>>> +ÂÂÂÂÂÂÂ }
>>>>> +ÂÂÂ }
>>>>> +
>>>>> +ÂÂÂ cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂÂÂ tegra_timer_stop);
>>>>> +
>>>>> +ÂÂÂ return ret;
>>>>> +
>>>>> +out_irq:
>>>>> +ÂÂÂ for_each_possible_cpu(cpu) {
>>>>> +ÂÂÂÂÂÂÂ struct timer_of *cpu_to;
>>>>> +
>>>>> +ÂÂÂÂÂÂÂ cpu_to = per_cpu_ptr(&tegra_to, cpu);
>>>>> +ÂÂÂÂÂÂÂ if (cpu_to->clkevt.irq) {
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
>>>>> +ÂÂÂÂÂÂÂÂÂÂÂ irq_dispose_mapping(cpu_to->clkevt.irq);
>>>>> +ÂÂÂÂÂÂÂ }
>>>>> ÂÂÂÂÂ }
>>>>> +out:
>>>>> +ÂÂÂ timer_of_cleanup(to);
>>>>> +ÂÂÂ return ret;
>>>>> +}
>>>>> +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_timer_init);
>>>>> +#else /* CONFIG_ARM */
>>>>> +static int __init tegra20_init_timer(struct device_node *np)
>>>>> +{
>>>> What about T132? Isn't it ARM64 which uses tegra20-timer IP? At least T132 DT suggests so and seems this change will break it.
>>>>
>>>> [snip]
>>>>
>>>
>>> Ah, noticed the "depends on ARM" in Kconfig.. Seems okay then.
>>>
>>
>>
>> This is a good point, because even though we had 'depends on ARM', this
>> still means that the Tegra132 DT is incorrect.
>>
>> Joseph, can you take a quick look at Tegra132?
>
> Hi Jon and Dmitry,
>
> No worry about T132, T132 uses arch timer (v7). The tegra20 timer driver has never been used. We should fix the dtsi file later.

Hi Joseph,

So is T132 HW actually incompatible with the tegra20-timer? If it's compatible, then I think the driver's code should be made more universal to support T132.

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