Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock
From: Maxime Ripard
Date: Wed Feb 06 2019 - 10:52:33 EST
On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > all of them, except the HRTIMER, expect the clock rate to stay
> > > the same and not change underneath them. And SATA expects it to
> > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > reduced rate of 50 MHz just fine.
> > >
> > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > should be using the old code (now in the if conditional block),
> > > i.e. the behavior should not have changed.
> > >
> > > I don't think this actually "fixes" whatever bug was introduced,
> > > but only papers over the issue, and possible introduces further
> > > issues for other users.
> > You're right, I've overlooked that it was pll-periph being
> > affected. I've dropped it for now.
> Any ideas what could be done. I currently have no time to debug it,
> but it affects existing systems.
I can't find what would change with that commit either if the flag
isn't set, so looking at the register state before and after that
commit would help I guess?
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
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