Hi Jeffrey,
On 07/02/19 8:22 PM, Jeffrey Hugo wrote:
On 2/7/2019 1:50 AM, Alim Akhtar wrote:OK, that's again implementation dependent and your platform used that
Hi Marc,
On 06/02/19 9:22 PM, Marc Gonzalez wrote:
On 06/02/2019 16:27, Alim Akhtar wrote:RST_N is the reset logic for UFS device core logic and it is input to
On 06/02/19 8:29 PM, Marc Gonzalez wrote:
[ÂÂÂ 2.405734] regulator_disable: ENTER vdd_l26
[ÂÂÂ 2.405958] regulator_disable: EXIT vdd_l26
[ÂÂÂ 2.406032]ÂÂ regulator_set_load: vdd_l26 = 0 uA
[ÂÂÂ 3.930447] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode
0x04 for idn 13 failed, index 0, err = -11
[ÂÂÂ 5.434358] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode
0x04 for idn 13 failed, index 0, err = -11
[ÂÂÂ 6.938318] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr: opcode
0x04 for idn 13 failed, index 0, err = -11
[ÂÂÂ 6.938414] ufshcd-qcom 1da4000.ufshc: ufshcd_query_attr_retry:
query attribute, idn 13, failed with error -11 after 3 retires
[ÂÂÂ 6.946959] ufshcd-qcom 1da4000.ufshc:
ufshcd_disable_auto_bkops: failed to enable exception event -11
[ÂÂÂ 6.958523] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id
0x1587 failed 3 retries
[ÂÂÂ 6.967730] ufshcd-qcom 1da4000.ufshc: dme-peer-get: attr-id
0x1586 failed 3 retries
[ÂÂÂ 6.975576] ufshcd-qcom 1da4000.ufshc: ufshcd_get_max_pwr_mode:
invalid max pwm tx gear read = 0
[ÂÂÂ 6.983306] ufshcd-qcom 1da4000.ufshc: ufshcd_probe_hba: Failed
getting max supported power mode
[ÂÂÂ 8.506314] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag:
Sending flag query for idn 3 failed, err = -11
[ÂÂ 10.010352] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag:
Sending flag query for idn 3 failed, err = -11
[ÂÂ 11.514313] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag:
Sending flag query for idn 3 failed, err = -11
[ÂÂ 11.514412] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry:
query attribute, opcode 5, idn 3, failed with error -11 after 3
retires
[ÂÂ 13.050354] ufshcd-qcom 1da4000.ufshc:
__ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0,
err = -11
[ÂÂ 14.554313] ufshcd-qcom 1da4000.ufshc:
__ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0,
err = -11
[ÂÂ 16.058313] ufshcd-qcom 1da4000.ufshc:
__ufshcd_query_descriptor: opcode 0x01 for idn 8 failed, index 0,
err = -11
[ÂÂ 16.058421] ufshcd-qcom 1da4000.ufshc: ufshcd_read_desc_param:
Failed reading descriptor. desc_id 8, desc_index 0, param_offset 0,
ret -11
[ÂÂ 16.067654] ufshcd-qcom 1da4000.ufshc: ufshcd_init_icc_levels:
Failed reading power descriptor.len = 98 ret = -11
[ÂÂ 37.074334] ufshcd-qcom 1da4000.ufshc: link startup failed 1
Can you check if your UFS device RESET_N is asserted correctly. It
might
be connected to some regulator and may be you can try keeping that
regulator as "regulator-always-on" from your DT node.
How do I check RESET_N? In software or hardware?
the device from UFS host controller.So, in your platform please check if
this line somehow connected to (pulled up) a PMIC supply. If that is the
case, please keep that regulator ON and see if this issue is resolved.
The reset line is routed though the global clock controller (GCC), and
must be explicitly asserted within the GCC to trigger a reset. As far
as I am aware, Linux is not touching this.
Additionally, I fail to see how if this was a reset issue, reverting
60f0187031c0 would have any impact (which doing so addresses our issue)
way. My point was to make sure that reset part is ok, if reset/power is
not proper to the UFS device core logic this kind of issues comes.
The evidence seems simple. We have properly described in DT all the regulators that are consumed by the UFS host controller, and by extension, the UFS storage chip as well.
In theory may be true. But looks like we dont have a solid evidence yetDo you think it is not a good idea to revertPlease hold on till we understand the real cause of this issue. Or we
60f0187031c05e04cbadffb62f557d0ff3564490 ?
have a consensuses for reverting the said commit.
Thanks!
Did you see https://lkml.org/lkml/2019/2/5/659 where I indicated VCCQ
powers components within the host controller, and by not setting load on
the regulator properly, we are likely undervolting those components due
to the current draw?
(correct me if I am wrong or misunderstood anything here
So that means its some short of hardware/board quirk, right?
Can you please recheck the schematic and see what Bjorn is telling
(about having right entries in the DT for regulator) resolve your issue?
Marc, Can you disabled pmic on that board (hope your board boots with
default PMIC supply) and see if this issue still occurs?
I am just trying to understand and see what is the real cause.
@Yaniv Gardi, will you be able to comment on reason for adding
60f0187031c05e04cbadffb62f557d0ff3564490 (any issue faced)?