Re: [RFC PATCH] clk: sunxi-ng: sun4i: Use CLK_SET_RATE_PARENT for mmc2 clock

[Priit Laes]

On Mon, Feb 11, 2019 at 04:34:02PM +0100, Maxime Ripard wrote:
> On Mon, Feb 11, 2019 at 02:35:52PM +0000, Priit Laes wrote:
> > On Wed, Feb 06, 2019 at 04:52:27PM +0100, Maxime Ripard wrote:
> > > Hi,
> > > 
> > > On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > > > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > > > > all of them, except the HRTIMER, expect the clock rate to stay
> > > > > > the same and not change underneath them. And SATA expects it to
> > > > > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > > > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > > > > reduced rate of 50 MHz just fine.
> > > > > > 
> > > > > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > > > > should be using the old code (now in the if conditional block),
> > > > > > i.e. the behavior should not have changed.
> > > > > > 
> > > > > > I don't think this actually "fixes" whatever bug was introduced,
> > > > > > but only papers over the issue, and possible introduces further
> > > > > > issues for other users.
> > > > > 
> > > > > You're right, I've overlooked that it was pll-periph being
> > > > > affected. I've dropped it for now.
> > > > 
> > > > Any ideas what could be done. I currently have no time to debug it,
> > > > but it affects existing systems.
> > > 
> > > I can't find what would change with that commit either if the flag
> > > isn't set, so looking at the register state before and after that
> > > commit would help I guess?
> > 
> > Register dump without the patch:
> > 
> > $ busybox devmem 0x01c20090
> > 0x0250030E
> > 
> > pll-ddr-base     2 2 0   768000000          0     0  50000
> >    pll-ddr-other 1 1 0   768000000          0     0  50000
> >       mmc2       3 3 0    51200000          0     0  50000
> > 
> > Register dump with patch applied, booted from mmc0 and after mounting emmc:
> > 
> > $ busybox devmem 0x01c20090
> > 0x8140020B
> > 
> > pll-periph-base  3 3 0  1200000000          0     0  50000
> >    pll-periph    6 6 0   600000000          0     0  50000
> >       mmc2       3 3 0    50000000          0     0  50000
> 
> I meant the whole Clock controller, ideally a diff between the two
> states would be great.

I have uploaded the raw files here:
https://gist.github.com/plaes/3465386d8aa55fa70fd3997310719828

The test scenario is following:

1) Boot via FEL (u-boot + zImage + boot.scr) and load root fs from
sd-card / mmc0

2) ssh into machine and dump register space

- no-patch-before-mount.dump
- no-patch-post-mount.dump

3) Attempt to mount emmc / mmc2 and dump ccu register space
- with-patch-before-mount.dump
- with-patch-post-mount.dump


Firstly, I noticed that first 0x200 bits are mirrored:
0x1c20000 = 0x1c20200
0x1c20004 = 0x1c20204
...
01xc201fc = 0x1c203fc

And here come the diffs:

a) Diff before mount vs patch / reverted patch:

mmc2:
  -0x1c20090: 0x0250030E
  +0x1c20090: 0x0140020B
unk1: (mirrored ahb?, this one's flaky due to mmc runtime suspend)
  -0x1c20260: 0x1200C17F
  +0x1c20260: 0x1200C07F
unk2: (mirrored mmc2?)
  -0x1c20290: 0x0250030E
  +0x1c20290: 0x0140020B

b) Diff post-mount vs patch / reverted patch:

ahb (this one's flaky, possibly due to runtime suspend for mmc):
  -0x1c20060: 0x1200C07F or 0x1200C17F
  +0x1c20060: 0x1200C47F
mmc2:
  -0x1c20090: 0x0250030E
  +0x1c20090: 0x8140020B
unk1:
  -0x1c20260: 0x1200C07F
  +0x1c20260: 0x1200C47F
unk3:
  -0x1c20288: 0x8140030B
  +0x1c20288: 0x0140030B
unk2: (mirrored mmc2?)
  -0x1c20290: 0x0250030E
  +0x1c20290: 0x8140020B