Re: [PATCH net-next 3/4] net: phy: Extract genphy_c45_pma_read_abilities from marvell10g
From: Andrew Lunn
Date: Tue Feb 12 2019 - 16:11:29 EST
On Mon, Feb 11, 2019 at 03:25:28PM +0100, Maxime Chevallier wrote:
> Marvell 10G PHY driver has a generic way of initializing the supported
> link modes by reading the PHY's C45 PMA abilities. This can be made
> generic, since these registers are part of the 802.3 specifications.
> This commit extracts the config_init link_mode initialization code from
> marvell10g and uses it to introduce the genphy_c45_pma_read_abilities
> Only PMA modes are read, it's still up to the caller to set the Pause
> Signed-off-by: Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx>
Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
> - __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
> - __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
> + __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
> + __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
I think someone already pointed out, this is not ideal. The PHY driver
should only set pause bits, if it needs odd pause settings because of
HW limitations. If no bits are set, the core will set both bits.
But this is not a new problem introduced by this patch, so it can be
fixed later, rather than hold up this patchset.