Re: [PATCH V6 2/7] clocksource: tegra: add Tegra210 timer support
From: Joseph Lo
Date: Wed Feb 13 2019 - 04:09:04 EST
On 2/13/19 4:55 PM, Daniel Lezcano wrote:
On 08/02/2019 14:23, Joseph Lo wrote:
Hi Daniel & Thomas,
Do we have the chance to get this patch merged for K5.1?
Hi Jospeh,
sorry for the delay, I was overbooked these past two weeks.
Overall it looks ok but give me a couple of days to review the driver
more deeply.
No problem, thanks.
On 2/2/19 12:16 AM, Joseph Lo wrote:
Add support for the Tegra210 timer that runs at oscillator clock
(TMR10-TMR13). We need these timers to work as clock event device and to
replace the ARMv8 architected timer due to it can't survive across the
power cycle of the CPU core or CPUPORESET signal. So it can't be a
wake-up
source when CPU suspends in power down state.
Also convert the original driver to use timer-of API.
Cc: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: linux-kernel@xxxxxxxxxxxxxxx
Signed-off-by: Joseph Lo <josephl@xxxxxxxxxx>
Acked-by: Thierry Reding <treding@xxxxxxxxxx>
Acked-by: Jon Hunter <jonathanh@xxxxxxxxxx>
---
v6:
 * refine the timer defines
 * add ack tag from Jon.
v5:
 * add ack tag from Thierry
v4:
 * merge timer-tegra210.c in previous version into timer-tegra20.c
v3:
 * use timer-of API
v2:
 * add error clean-up code
---
 drivers/clocksource/Kconfig | 2 +-
 drivers/clocksource/timer-tegra20.c | 371 ++++++++++++++++++++--------
 include/linux/cpuhotplug.h | 1 +
 3 files changed, 270 insertions(+), 104 deletions(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index a9e26f6a81a1..6af78534a285 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,7 +131,7 @@ config SUN5I_HSTIMER
 config TEGRA_TIMER
ÂÂÂÂÂ bool "Tegra timer driver" if COMPILE_TEST
ÂÂÂÂÂ select CLKSRC_MMIO
-ÂÂÂ depends on ARM
+ÂÂÂ select TIMER_OF
ÂÂÂÂÂ help
ÂÂÂÂÂÂÂ Enables support for the Tegra driver.
 diff --git a/drivers/clocksource/timer-tegra20.c
b/drivers/clocksource/timer-tegra20.c
index 4293943f4e2b..f66edd63d7f4 100644
--- a/drivers/clocksource/timer-tegra20.c
+++ b/drivers/clocksource/timer-tegra20.c
@@ -15,21 +15,24 @@
ÂÂ *
ÂÂ */
 -#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/sched_clock.h>
-#include <linux/delay.h>
+#include <linux/percpu.h>
+#include <linux/syscore_ops.h>
+#include <linux/time.h>
+
+#include "timer-of.h"
 +#ifdef CONFIG_ARM
 #include <asm/mach/time.h>
+#endif
  #define RTC_SECONDS 0x08
 #define RTC_SHADOW_SECONDS 0x0c
@@ -39,74 +42,145 @@
 #define TIMERUS_USEC_CFG 0x14
 #define TIMERUS_CNTR_FREEZE 0x4c
 -#define TIMER1_BASE 0x0
-#define TIMER2_BASE 0x8
-#define TIMER3_BASE 0x50
-#define TIMER4_BASE 0x58
-
-#define TIMER_PTV 0x0
-#define TIMER_PCR 0x4
-
+#define TIMER_PTVÂÂÂÂÂÂÂ 0x0
+#define TIMER_PTV_ENÂÂÂÂÂÂÂ BIT(31)
+#define TIMER_PTV_PERÂÂÂÂÂÂÂ BIT(30)
+#define TIMER_PCRÂÂÂÂÂÂÂ 0x4
+#define TIMER_PCR_INTR_CLRÂÂÂ BIT(30)
+
+#ifdef CONFIG_ARM
+#define TIMER_CPU0ÂÂÂÂÂÂÂ 0x50 /* TIMER3 */
+#else
+#define TIMER_CPU0ÂÂÂÂÂÂÂ 0x90 /* TIMER10 */
+#define TIMER10_IRQ_IDXÂÂÂÂÂÂÂ 10
+#define IRQ_IDX_FOR_CPU(cpu)ÂÂÂ (TIMER10_IRQ_IDX + cpu)
+#endif
+#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
+
+static u32 usec_config;
 static void __iomem *timer_reg_base;
+#ifdef CONFIG_ARM
 static void __iomem *rtc_base;
-
 static struct timespec64 persistent_ts;
 static u64 persistent_ms, last_persistent_ms;
-
 static struct delay_timer tegra_delay_timer;
-
-#define timer_writel(value, reg) \
-ÂÂÂ writel_relaxed(value, timer_reg_base + (reg))
-#define timer_readl(reg) \
-ÂÂÂ readl_relaxed(timer_reg_base + (reg))
+#endif
  static int tegra_timer_set_next_event(unsigned long cycles,
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ struct clock_event_device *evt)
 {
-ÂÂÂ u32 reg;
+ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
-ÂÂÂ timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+ÂÂÂ writel(TIMER_PTV_EN |
+ÂÂÂÂÂÂÂÂÂÂ ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
+ÂÂÂÂÂÂÂÂÂÂ reg_base + TIMER_PTV);
 Â return 0;
 }
 -static inline void timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_shutdown(struct clock_event_device *evt)
 {
-ÂÂÂ timer_writel(0, TIMER3_BASE + TIMER_PTV);
+ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ÂÂÂ writel(0, reg_base + TIMER_PTV);
+
+ÂÂÂ return 0;
 }
 -static int tegra_timer_shutdown(struct clock_event_device *evt)
+static int tegra_timer_set_periodic(struct clock_event_device *evt)
 {
-ÂÂÂ timer_shutdown(evt);
+ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ÂÂÂ writel(TIMER_PTV_EN | TIMER_PTV_PER |
+ÂÂÂÂÂÂÂÂÂÂ ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
+ÂÂÂÂÂÂÂÂÂÂ reg_base + TIMER_PTV);
+
ÂÂÂÂÂ return 0;
 }
 -static int tegra_timer_set_periodic(struct clock_event_device *evt)
+static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
 {
-ÂÂÂ u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
+ÂÂÂ struct clock_event_device *evt = (struct clock_event_device
*)dev_id;
+ÂÂÂ void __iomem *reg_base = timer_of_base(to_timer_of(evt));
+
+ÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ÂÂÂ evt->event_handler(evt);
+
+ÂÂÂ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_ARM64
+static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
+ÂÂÂ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
+
+ÂÂÂ .clkevt = {
+ÂÂÂÂÂÂÂ .name = "tegra_timer",
+ÂÂÂÂÂÂÂ .rating = 460,
+ÂÂÂÂÂÂÂ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ÂÂÂÂÂÂÂ .set_next_event = tegra_timer_set_next_event,
+ÂÂÂÂÂÂÂ .set_state_shutdown = tegra_timer_shutdown,
+ÂÂÂÂÂÂÂ .set_state_periodic = tegra_timer_set_periodic,
+ÂÂÂÂÂÂÂ .set_state_oneshot = tegra_timer_shutdown,
+ÂÂÂÂÂÂÂ .tick_resume = tegra_timer_shutdown,
+ÂÂÂ },
+};
+
+static int tegra_timer_setup(unsigned int cpu)
+{
+ÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+ÂÂÂ irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
+ÂÂÂ enable_irq(to->clkevt.irq);
+
+ÂÂÂ clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1, /* min */
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x1fffffff); /* 29 bits */
 - timer_shutdown(evt);
-ÂÂÂ timer_writel(reg, TIMER3_BASE + TIMER_PTV);
ÂÂÂÂÂ return 0;
 }
 -static struct clock_event_device tegra_clockevent = {
-ÂÂÂ .nameÂÂÂÂÂÂÂÂÂÂÂ = "timer0",
-ÂÂÂ .ratingÂÂÂÂÂÂÂÂÂÂÂ = 300,
-ÂÂÂ .featuresÂÂÂÂÂÂÂ = CLOCK_EVT_FEAT_ONESHOT |
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_PERIODIC |
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_DYNIRQ,
-ÂÂÂ .set_next_eventÂÂÂÂÂÂÂ = tegra_timer_set_next_event,
-ÂÂÂ .set_state_shutdownÂÂÂ = tegra_timer_shutdown,
-ÂÂÂ .set_state_periodicÂÂÂ = tegra_timer_set_periodic,
-ÂÂÂ .set_state_oneshotÂÂÂ = tegra_timer_shutdown,
-ÂÂÂ .tick_resumeÂÂÂÂÂÂÂ = tegra_timer_shutdown,
+static int tegra_timer_stop(unsigned int cpu)
+{
+ÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+
+ÂÂÂ to->clkevt.set_state_shutdown(&to->clkevt);
+ÂÂÂ disable_irq_nosync(to->clkevt.irq);
+
+ÂÂÂ return 0;
+}
+#else /* CONFIG_ARM */
+static struct timer_of tegra_to = {
+ÂÂÂ .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
+
+ÂÂÂ .clkevt = {
+ÂÂÂÂÂÂÂ .name = "tegra_timer",
+ÂÂÂÂÂÂÂ .ratingÂÂÂ = 300,
+ÂÂÂÂÂÂÂ .features = CLOCK_EVT_FEAT_ONESHOT |
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_PERIODIC |
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ CLOCK_EVT_FEAT_DYNIRQ,
+ÂÂÂÂÂÂÂ .set_next_eventÂÂÂ = tegra_timer_set_next_event,
+ÂÂÂÂÂÂÂ .set_state_shutdown = tegra_timer_shutdown,
+ÂÂÂÂÂÂÂ .set_state_periodic = tegra_timer_set_periodic,
+ÂÂÂÂÂÂÂ .set_state_oneshot = tegra_timer_shutdown,
+ÂÂÂÂÂÂÂ .tick_resume = tegra_timer_shutdown,
+ÂÂÂÂÂÂÂ .cpumask = cpu_possible_mask,
+ÂÂÂ },
+
+ÂÂÂ .of_irq = {
+ÂÂÂÂÂÂÂ .index = 2,
+ÂÂÂÂÂÂÂ .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
+ÂÂÂÂÂÂÂ .handler = tegra_timer_isr,
+ÂÂÂ },
 };
  static u64 notrace tegra_read_sched_clock(void)
 {
-ÂÂÂ return timer_readl(TIMERUS_CNTR_1US);
+ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
+}
+
+static unsigned long tegra_delay_timer_read_counter_long(void)
+{
+ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
 }
  /*
@@ -143,98 +217,188 @@ static void
tegra_read_persistent_clock64(struct timespec64 *ts)
ÂÂÂÂÂ timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
ÂÂÂÂÂ *ts = persistent_ts;
 }
+#endif
 -static unsigned long tegra_delay_timer_read_counter_long(void)
+static int tegra_timer_suspend(void)
 {
-ÂÂÂ return readl(timer_reg_base + TIMERUS_CNTR_1US);
+#ifdef CONFIG_ARM64
+ÂÂÂ int cpu;
+
+ÂÂÂ for_each_possible_cpu(cpu) {
+ÂÂÂÂÂÂÂ struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
+ÂÂÂÂÂÂÂ void __iomem *reg_base = timer_of_base(to);
+
+ÂÂÂÂÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+ÂÂÂ }
+#else
+ÂÂÂ void __iomem *reg_base = timer_of_base(&tegra_to);
+
+ÂÂÂ writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
+#endif
+
+ÂÂÂ return 0;
 }
 -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
+static void tegra_timer_resume(void)
 {
-ÂÂÂ struct clock_event_device *evt = (struct clock_event_device
*)dev_id;
-ÂÂÂ timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
-ÂÂÂ evt->event_handler(evt);
-ÂÂÂ return IRQ_HANDLED;
+ÂÂÂ writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
 }
 -static struct irqaction tegra_timer_irq = {
-ÂÂÂ .nameÂÂÂÂÂÂÂ = "timer0",
-ÂÂÂ .flagsÂÂÂÂÂÂÂ = IRQF_TIMER | IRQF_TRIGGER_HIGH,
-ÂÂÂ .handlerÂÂÂ = tegra_timer_interrupt,
-ÂÂÂ .dev_idÂÂÂÂÂÂÂ = &tegra_clockevent,
+static struct syscore_ops tegra_timer_syscore_ops = {
+ÂÂÂ .suspend = tegra_timer_suspend,
+ÂÂÂ .resume = tegra_timer_resume,
 };
 -static int __init tegra20_init_timer(struct device_node *np)
+static int tegra_timer_init(struct device_node *np, struct timer_of *to)
 {
-ÂÂÂ struct clk *clk;
-ÂÂÂ unsigned long rate;
-ÂÂÂ int ret;
+ÂÂÂ int ret = 0;
 - timer_reg_base = of_iomap(np, 0);
-ÂÂÂ if (!timer_reg_base) {
-ÂÂÂÂÂÂÂ pr_err("Can't map timer registers\n");
-ÂÂÂÂÂÂÂ return -ENXIO;
-ÂÂÂ }
+ÂÂÂ ret = timer_of_init(np, to);
+ÂÂÂ if (ret < 0)
+ÂÂÂÂÂÂÂ goto out;
 - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
-ÂÂÂ if (tegra_timer_irq.irq <= 0) {
-ÂÂÂÂÂÂÂ pr_err("Failed to map timer IRQ\n");
-ÂÂÂÂÂÂÂ return -EINVAL;
-ÂÂÂ }
+ÂÂÂ timer_reg_base = timer_of_base(to);
 - clk = of_clk_get(np, 0);
-ÂÂÂ if (IS_ERR(clk)) {
-ÂÂÂÂÂÂÂ pr_warn("Unable to get timer clock. Assuming 12Mhz input
clock.\n");
-ÂÂÂÂÂÂÂ rate = 12000000;
-ÂÂÂ } else {
-ÂÂÂÂÂÂÂ clk_prepare_enable(clk);
-ÂÂÂÂÂÂÂ rate = clk_get_rate(clk);
-ÂÂÂ }
-
-ÂÂÂ switch (rate) {
+ÂÂÂ /*
+ÂÂÂÂ * Configure microsecond timers to have 1MHz clock
+ÂÂÂÂ * Config register is 0xqqww, where qq is "dividend", ww is
"divisor"
+ÂÂÂÂ * Uses n+1 scheme
+ÂÂÂÂ */
+ÂÂÂ switch (timer_of_rate(to)) {
ÂÂÂÂÂ case 12000000:
-ÂÂÂÂÂÂÂ timer_writel(0x000b, TIMERUS_USEC_CFG);
+ÂÂÂÂÂÂÂ usec_config = 0x000b; /* (11+1)/(0+1) */
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case 12800000:
+ÂÂÂÂÂÂÂ usec_config = 0x043f; /* (63+1)/(4+1) */
ÂÂÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ case 13000000:
-ÂÂÂÂÂÂÂ timer_writel(0x000c, TIMERUS_USEC_CFG);
+ÂÂÂÂÂÂÂ usec_config = 0x000c; /* (12+1)/(0+1) */
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case 16800000:
+ÂÂÂÂÂÂÂ usec_config = 0x0453; /* (83+1)/(4+1) */
ÂÂÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ case 19200000:
-ÂÂÂÂÂÂÂ timer_writel(0x045f, TIMERUS_USEC_CFG);
+ÂÂÂÂÂÂÂ usec_config = 0x045f; /* (95+1)/(4+1) */
ÂÂÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ case 26000000:
-ÂÂÂÂÂÂÂ timer_writel(0x0019, TIMERUS_USEC_CFG);
+ÂÂÂÂÂÂÂ usec_config = 0x0019; /* (25+1)/(0+1) */
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case 38400000:
+ÂÂÂÂÂÂÂ usec_config = 0x04bf; /* (191+1)/(4+1) */
+ÂÂÂÂÂÂÂ break;
+ÂÂÂ case 48000000:
+ÂÂÂÂÂÂÂ usec_config = 0x002f; /* (47+1)/(0+1) */
ÂÂÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ default:
-ÂÂÂÂÂÂÂ WARN(1, "Unknown clock rate");
+ÂÂÂÂÂÂÂ ret = -EINVAL;
+ÂÂÂÂÂÂÂ goto out;
+ÂÂÂ }
+
+ÂÂÂ writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
+
+ÂÂÂ register_syscore_ops(&tegra_timer_syscore_ops);
+out:
+ÂÂÂ return ret;
+}
+
+#ifdef CONFIG_ARM64
+static int __init tegra210_timer_init(struct device_node *np)
+{
+ÂÂÂ int cpu, ret = 0;
+ÂÂÂ struct timer_of *to;
+
+ÂÂÂ to = this_cpu_ptr(&tegra_to);
+ÂÂÂ ret = tegra_timer_init(np, to);
+ÂÂÂ if (ret < 0)
+ÂÂÂÂÂÂÂ goto out;
+
+ÂÂÂ for_each_possible_cpu(cpu) {
+ÂÂÂÂÂÂÂ struct timer_of *cpu_to;
+
+ÂÂÂÂÂÂÂ cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ÂÂÂÂÂÂÂ cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
+ÂÂÂÂÂÂÂ cpu_to->of_clk.rate = timer_of_rate(to);
+ÂÂÂÂÂÂÂ cpu_to->clkevt.cpumask = cpumask_of(cpu);
+
+ÂÂÂÂÂÂÂ cpu_to->clkevt.irq =
+ÂÂÂÂÂÂÂÂÂÂÂ irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
+ÂÂÂÂÂÂÂ if (!cpu_to->clkevt.irq) {
+ÂÂÂÂÂÂÂÂÂÂÂ pr_err("%s: can't map IRQ for CPU%d\n",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ __func__, cpu);
+ÂÂÂÂÂÂÂÂÂÂÂ ret = -EINVAL;
+ÂÂÂÂÂÂÂÂÂÂÂ goto out;
+ÂÂÂÂÂÂÂ }
+
+ÂÂÂÂÂÂÂ irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
+ÂÂÂÂÂÂÂ ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ IRQF_TIMER | IRQF_NOBALANCING,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ cpu_to->clkevt.name, &cpu_to->clkevt);
+ÂÂÂÂÂÂÂ if (ret) {
+ÂÂÂÂÂÂÂÂÂÂÂ pr_err("%s: cannot setup irq %d for CPU%d\n",
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ __func__, cpu_to->clkevt.irq, cpu);
+ÂÂÂÂÂÂÂÂÂÂÂ ret = -EINVAL;
+ÂÂÂÂÂÂÂÂÂÂÂ goto out_irq;
+ÂÂÂÂÂÂÂ }
+ÂÂÂ }
+
+ÂÂÂ cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂ "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂ tegra_timer_stop);
+
+ÂÂÂ return ret;
+
+out_irq:
+ÂÂÂ for_each_possible_cpu(cpu) {
+ÂÂÂÂÂÂÂ struct timer_of *cpu_to;
+
+ÂÂÂÂÂÂÂ cpu_to = per_cpu_ptr(&tegra_to, cpu);
+ÂÂÂÂÂÂÂ if (cpu_to->clkevt.irq) {
+ÂÂÂÂÂÂÂÂÂÂÂ free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
+ÂÂÂÂÂÂÂÂÂÂÂ irq_dispose_mapping(cpu_to->clkevt.irq);
+ÂÂÂÂÂÂÂ }
ÂÂÂÂÂ }
+out:
+ÂÂÂ timer_of_cleanup(to);
+ÂÂÂ return ret;
+}
+TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer",
tegra210_timer_init);
+#else /* CONFIG_ARM */
+static int __init tegra20_init_timer(struct device_node *np)
+{
+ÂÂÂ int ret = 0;
+
+ÂÂÂ ret = tegra_timer_init(np, &tegra_to);
+ÂÂÂ if (ret < 0)
+ÂÂÂÂÂÂÂ goto out;
 - sched_clock_register(tegra_read_sched_clock, 32, 1000000);
+ÂÂÂ tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
+ÂÂÂ tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 + sched_clock_register(tegra_read_sched_clock, 32,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timer_of_rate(&tegra_to));
ÂÂÂÂÂ ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "timer_us", 1000000, 300, 32,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ clocksource_mmio_readl_up);
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ "timer_us", timer_of_rate(&tegra_to),
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 300, 32, clocksource_mmio_readl_up);
ÂÂÂÂÂ if (ret) {
ÂÂÂÂÂÂÂÂÂ pr_err("Failed to register clocksource\n");
-ÂÂÂÂÂÂÂ return ret;
+ÂÂÂÂÂÂÂ goto out;
ÂÂÂÂÂ }
 Â tegra_delay_timer.read_current_timer =
ÂÂÂÂÂÂÂÂÂÂÂÂÂ tegra_delay_timer_read_counter_long;
-ÂÂÂ tegra_delay_timer.freq = 1000000;
+ÂÂÂ tegra_delay_timer.freq = timer_of_rate(&tegra_to);
ÂÂÂÂÂ register_current_timer_delay(&tegra_delay_timer);
 - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-ÂÂÂ if (ret) {
-ÂÂÂÂÂÂÂ pr_err("Failed to register timer IRQ: %d\n", ret);
-ÂÂÂÂÂÂÂ return ret;
-ÂÂÂ }
+ÂÂÂ clockevents_config_and_register(&tegra_to.clkevt,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ timer_of_rate(&tegra_to),
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x1,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x1fffffff);
 - tegra_clockevent.cpumask = cpu_possible_mask;
-ÂÂÂ tegra_clockevent.irq = tegra_timer_irq.irq;
-ÂÂÂ clockevents_config_and_register(&tegra_clockevent, 1000000,
-ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 0x1, 0x1fffffff);
+ÂÂÂ return ret;
+out:
+ÂÂÂ timer_of_cleanup(&tegra_to);
 - return 0;
+ÂÂÂ return ret;
 }
 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer",
tegra20_init_timer);
 @@ -261,3 +425,4 @@ static int __init tegra20_init_rtc(struct
device_node *np)
ÂÂÂÂÂ return register_persistent_clock(tegra_read_persistent_clock64);
 }
 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
+#endif
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index fd586d0301e7..e78281d07b70 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -121,6 +121,7 @@ enum cpuhp_state {
ÂÂÂÂÂ CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING,
ÂÂÂÂÂ CPUHP_AP_ARM_TWD_STARTING,
ÂÂÂÂÂ CPUHP_AP_QCOM_TIMER_STARTING,
+ÂÂÂ CPUHP_AP_TEGRA_TIMER_STARTING,
ÂÂÂÂÂ CPUHP_AP_ARMADA_TIMER_STARTING,
ÂÂÂÂÂ CPUHP_AP_MARCO_TIMER_STARTING,
ÂÂÂÂÂ CPUHP_AP_MIPS_GIC_TIMER_STARTING,