Re: [PATCH v2 2/3] clk: at91: sckc: add support for SAM9X60

[Claudiu.Beznea]

On 18.02.2019 23:20, Alexandre Belloni wrote:
> On 14/02/2019 12:14:32+0000, Claudiu.Beznea@xxxxxxxxxxxxx wrote:
>> From: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
>>
>> Add support for SAM9X60.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
>> ---
>>  drivers/clk/at91/sckc.c | 30 ++++++++++++++++++++++++++++++
>>  1 file changed, 30 insertions(+)
>>
>> diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
>> index b7163d3a2269..b3075c51d260 100644
>> --- a/drivers/clk/at91/sckc.c
>> +++ b/drivers/clk/at91/sckc.c
>> @@ -459,6 +459,36 @@ static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
>>  CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
>>  	       of_at91sam9x5_sckc_setup);
>>  
>> +static const struct clk_slow_offsets at91sam9x60_offsets = {
>> +	.cr_rcen = AT91_SCKC_OFFSET_INVALID,
>> +	.cr_osc32en = 1,
>> +	.cr_osc32byp = 2,
>> +	.cr_oscsel = 24,
>> +};
>> +
>> +static void __init of_at91sam9x60_sckc_setup(struct device_node *np)
>> +{
>> +	struct device_node *childnp;
>> +	void (*clk_setup)(struct device_node *np, void __iomem *io,
>> +			  const struct clk_slow_offsets *offsets);
>> +	const struct of_device_id *clk_id;
>> +	void __iomem *regbase = of_iomap(np, 0);
>> +
>> +	if (!regbase)
>> +		return;
>> +
>> +	for_each_child_of_node(np, childnp) {
>> +		clk_id = of_match_node(sckc_clk_ids, childnp);
>> +		if (!clk_id)
>> +			continue;
>> +		clk_setup = clk_id->data;
>> +		clk_setup(childnp, regbase, &at91sam9x60_offsets);
>> +	}
> 
> You actually need to have new bindings. The sam9x60 registration should
> look more like the sama5d4 registration. I have a rework for the sam9x5
> sckc that I will send this week to have a proper binding (i.e: no
> children).

Does this means that this would also solve the problem I tried to address
with this patch?

> 
> However, there is a fundamental change in the sam9x60, previously, the
> sckc had only one output clock. the sam9x60 has both td_slck and
> md_slck. Both need to be accessible because they are input to the PMC.

I was guided by the fact that md_slck is generated by the always on slow RC
oscillator (part of slow clock controller) and since there is no control
for it on slow clock controller there is no need to be described by this
driver.

> 
> This means you will have to register the sckc with of_clk_hw_onecell_get
> as the get callback.

Ok, I'll look into it.

> 
> We could still decide to do the same with sam9x5 even if it has only one
> output clock.
>