Re: [PATCH 6/8] phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY Driver

[Martin Blumenstingl]

Hi Neil,

On Tue, Feb 12, 2019 at 4:16 PM Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote:
>
> This adds support for the shared USB3 + PCIE PHY found in the
> Amlogic G12A SoC Family.
>
> It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
> the board.
>
> Selection is done by the #phy-cells, making the mode static and exclusive.
>
> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
> ---
>  drivers/phy/amlogic/Kconfig                   |  12 +
>  drivers/phy/amlogic/Makefile                  |   1 +
>  .../phy/amlogic/phy-meson-g12a-usb3-pcie.c    | 414 ++++++++++++++++++
>  3 files changed, 427 insertions(+)
>  create mode 100644 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
>
> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
> index 78d6e194dce9..7ccb9a756aba 100644
> --- a/drivers/phy/amlogic/Kconfig
> +++ b/drivers/phy/amlogic/Kconfig
> @@ -48,3 +48,15 @@ config PHY_MESON_G12A_USB2
>           Enable this to support the Meson USB2 PHYs found in Meson
>           G12A SoCs.
>           If unsure, say N.
> +
> +config PHY_MESON_G12A_USB3_PCIE
> +       tristate "Meson G12A USB3+PCIE Combo PHY drivers"
nit-pick: s/drivers/driver/

> +       default ARCH_MESON
> +       depends on OF && (ARCH_MESON || COMPILE_TEST)
> +       depends on USB_SUPPORT
> +       select GENERIC_PHY
> +       select REGMAP_MMIO
> +       help
> +         Enable this to support the Meson USB3 + PCIE Combi PHY found
> +         in Meson G12A SoCs.
> +         If unsure, say N.
> diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
> index 7d4d10f5a6b3..fdd008e1b19b 100644
> --- a/drivers/phy/amlogic/Makefile
> +++ b/drivers/phy/amlogic/Makefile
> @@ -2,3 +2,4 @@ obj-$(CONFIG_PHY_MESON8B_USB2)          += phy-meson8b-usb2.o
>  obj-$(CONFIG_PHY_MESON_GXL_USB2)       += phy-meson-gxl-usb2.o
>  obj-$(CONFIG_PHY_MESON_G12A_USB2)      += phy-meson-g12a-usb2.o
>  obj-$(CONFIG_PHY_MESON_GXL_USB3)       += phy-meson-gxl-usb3.o
> +obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
> new file mode 100644
> index 000000000000..59eae98928e9
> --- /dev/null
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
> @@ -0,0 +1,414 @@
[...]
> +static int phy_g12a_usb3_init(struct phy *phy)
> +{
> +       struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> +       int data, ret;
> +
> +       /* Switch PHY to USB3 */
> +       regmap_update_bits(priv->regmap, PHY_R0,
> +                          PHY_R0_PCIE_USB3_SWITCH,
> +                          PHY_R0_PCIE_USB3_SWITCH);
> +
> +       /*
> +        * WORKAROUND: There is SSPHY suspend bug due to
> +        * which USB enumerates
> +        * in HS mode instead of SS mode. Workaround it by asserting
> +        * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
> +        * mode
> +        */
> +       ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7));
does the datasheet have names for these registers / bits? it if does
then it would be great if you could introduce #defines for them

> +       if (ret)
> +               return ret;
> +
> +       ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * Fix RX Equalization setting as follows
> +        * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
> +        * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
> +        * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
> +        * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
> +        */
> +       ret = regmap_read(priv->regmap_cr, 0x1006, &data);
> +       if (ret)
> +               return ret;
> +
> +       data &= ~BIT(6);
> +       data |= BIT(7);
> +       data &= ~(0x7 << 8);
> +       data |= (0x3 << 8);
> +       data |= (1 << 11);
> +       ret = regmap_write(priv->regmap_cr, 0x1006, data);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * Set EQ and TX launch amplitudes as follows
> +        * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
> +        * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
> +        * LANE0.TX_OVRD_DRV_LO.EN set to 1.
> +        */
> +       ret = regmap_read(priv->regmap_cr, 0x1002, &data);
> +       if (ret)
> +               return ret;
> +
> +       data &= ~0x3f80;
> +       data |= (0x16 << 7);
> +       data &= ~0x7f;
> +       data |= (0x7f | BIT(14));
> +       ret = regmap_write(priv->regmap_cr, 0x1002, data);
> +       if (ret)
> +               return ret;
> +
> +       /*
> +        * MPLL_LOOP_CTL.PROP_CNTRL = 8
> +        */
why a multi-line comment here? "Switch PHY to USB3" above uses a
single-line comment

> +       ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4);
> +       if (ret)
> +               return ret;
> +
> +       regmap_update_bits(priv->regmap, PHY_R2,
> +                       PHY_R2_PHY_TX_VBOOST_LVL,
> +                       FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
> +
> +       regmap_update_bits(priv->regmap, PHY_R1,
> +                       PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
> +                       FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
> +                       FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
> +
> +       return 0;
> +}
> +
> +static int phy_g12a_usb3_pcie_init(struct phy *phy)
> +{
> +       struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> +       int ret;
> +
> +       ret = reset_control_reset(priv->reset);
> +       if (ret)
> +               return ret;
> +
> +       if (priv->mode == PHY_TYPE_USB3)
> +               return phy_g12a_usb3_init(phy);
> +
> +       /* Power UP PCIE */
> +       regmap_update_bits(priv->regmap, PHY_R0,
> +                          PHY_R0_PCIE_POWER_STATE,
> +                          FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
do we also need this for USB mode?
also do we need to change the PHY_R2 register values
(PHY_R2_PHY_TX_VBOOST_LVL for example) for PCIe, for example if the
bootloader initialized the PHY in USB3 mode while the board actually
exposes a PCIe port?


Regards
Martin