Re: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum 010001

[Catalin Marinas]

On Tue, Feb 26, 2019 at 06:43:41PM +0000, James Morse wrote:
> From: Zhang Lei <zhang.lei@xxxxxxxxxxxxxx>
> 
> On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may cause
> an undefined fault (Data abort, DFSC=0b111111). This fault occurs under
> a specific hardware condition when a load/store instruction performs an
> address translation. Any load/store instruction, except non-fault access
> including Armv8 and SVE might cause this undefined fault.
> 
> The TCR_ELx.NFD1 bit is used by the kernel when CONFIG_RANDOMIZE_BASE
> is enabled to mitigate timing attacks against KASLR where the kernel
> address space could be probed using the FFR and suppressed fault on
> SVE loads.
> 
> Since this erratum causes spurious exceptions, which may corrupt
> the exception registers, we clear the TCR_ELx.NFDx=1 bits when
> booting on an affected CPU.
> 
> Signed-off-by: Zhang Lei <zhang.lei@xxxxxxxxxxxxxx>
> [Generated MIDR value/mask for __cpu_setup(), removed spurious-fault handler
>  and always disabled the NFDx bits on affected CPUs]
> Signed-off-by: James Morse <james.morse@xxxxxxx>
> Tested-by: zhang.lei <zhang.lei@xxxxxxxxxxxxxx>

Queued for 5.1. Thanks.

-- 
Catalin