Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328

[Peter Geis]

On 3/10/2019 8:00 AM, Jonas Karlman wrote:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
>
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
>
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@xxxxxxxxx>

Tested on the rk3328-roc-cc.

Tested-by: Peter Geis <pgwipeout@xxxxxxxxx>

> ---
>   drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
> index faa94adb2a37..5f6b6bcc2149 100644
> --- a/drivers/clk/rockchip/clk-rk3328.c
> +++ b/drivers/clk/rockchip/clk-rk3328.c
> @@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 12, GFLAGS),
>   	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
> -			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
> +			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 4, GFLAGS),
>   	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
>   			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
> @@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
>   			RK3328_CLKGATE_CON(25), 1, GFLAGS),
>   	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 2, GFLAGS),
>   	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 3, GFLAGS),
>   	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 4, GFLAGS),
>   	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 5, GFLAGS),
>   	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 6, GFLAGS),
>   
>   	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
>   			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
> @@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_GMAC */
>   	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
> -			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
> +			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(3), 2, GFLAGS),
>   	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
>   			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
> @@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_PERI */
>   	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
> -	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
> +	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
>   
>   	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
>   	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
> @@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
>   				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
>   				     ARRAY_SIZE(rk3328_cpuclk_rates));
>   
> -	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
> +	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
>   				  ROCKCHIP_SOFTRST_HIWORD_MASK);
>   
>   	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);