Re: [RFC 1/2] dt-bindings: imx6q-pcie: Add support for i.MX8QM/QXP PCIe

[Lucas Stach]

Hi Richard,

Am Mittwoch, den 13.03.2019, 09:15 +0000 schrieb Richard Zhu:
> Add codes needed to support i.MX8QM/QXP PCIe.
> - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
> Â The PCIe and SATA modules are contained in the HSIO subsystem. There
> Â are two PCIe, one SATA controllers and three mixed lane PHYs on
> Â i.MX8QM. There are three use cases of the HSIO subsystem on i.MX8QM.
> Â 1. PCIea 2 lanes and one SATA AHCI port.
> Â 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
> Â 3. PCIea 2 lanes, PCIeb 1 lane.
> Â i.MX8QXP only has PCIeb controller and one lane PHY.
> Â Use the hsio-cfg property to specify the different modes.
> - The HSIO address map as viewed from system level is as shown below.
> Â address [31:24]ÂÂÂÂLocal addressÂÂÂÂTargetÂÂÂÂAddress Size
> Â 5FÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ0ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂHSIOÂÂÂÂÂÂ16MB
> Â 60-6FÂÂÂÂÂÂÂÂÂÂÂÂÂÂ40-4FÂÂÂÂÂÂÂÂÂÂÂÂHSIOÂÂÂÂÂÂ256MB
> Â 70-7FÂÂÂÂÂÂÂÂÂÂÂÂÂÂ80-8FÂÂÂÂÂÂÂÂÂÂÂÂHSIOÂÂÂÂÂÂ256MB
> Â The property local-addr is required to specify it.
> - Both external OSC and internal PLL can be used as PCIe reference
> Â clock, use the ext_osc property to distinguish them.
> - clock request GPIO for controlling the PCI reference clock request
> Â signal. And should be configure OD when L1SS maybe enabled later.
> - One more power domain HSIO_GPIO and clock PCIE_PER are required by
> Â i.MX8QM/QXP PCIe.
> Â Add these specific properties to enable i.MX8QM/QXP PCIe.

All this HSIO handling should move into a separate PHY driver. This has
nothing to do with the PCIe controller itself. See for example the
Tegra XUSB PHY driver (drivers/phy/tegra/xusb.c), which is a similar
combined PCIE/USB3/SATA PHY driver.

Regards,
Lucas

> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
> Â.../devicetree/bindings/pci/fsl,imx6q-pcie.txtÂÂÂÂÂÂ| 21 +++++++++++++++++++++
> Â1 file changed, 21 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index a7f5f5a..f7586c9 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -10,6 +10,8 @@ Required properties:
> > Â	- "fsl,imx6qp-pcie"
> > Â	- "fsl,imx7d-pcie"
> > Â	- "fsl,imx8mq-pcie"
> > +	- "fsl,imx8qm-pcie"
> > +	- "fsl,imx8qxp-pcie"
> Â- reg: base address and length of the PCIe controller
> Â- interrupts: A list of interrupt outputs of the controller. Must contain an
> ÂÂÂentry for each entry in the interrupt-names property.
> @@ -38,6 +40,10 @@ Optional properties:
> ÂÂÂThe regulator will be enabled when initializing the PCIe host and
> ÂÂÂdisabled either as part of the init process or when shutting down the
> ÂÂÂhost.
> +- clkreq-gpio: Should specify the GPIO for controlling the PCI reference clock
> +ÂÂrequest signal.
> +- ext_osc: External OSC is used as PCIe reference clock or not. 0: Internal
> +ÂÂPLL. 1: External OSC.
> Â
> ÂAdditional required properties for imx6sx-pcie:
> Â- clock names: Must include the following additional entries:
> @@ -60,6 +66,21 @@ Additional required properties for imx8mq-pcie:
> Â- clock-names: Must include the following additional entries:
> > Â	- "pcie_aux"
> Â
> +Additional required properties for imx8qm/qxp pcie:
> +- power-domains: Must be set to a phandle pointing to PCIE, PCIE_PHY power and
> +ÂÂHSIO_GPIO domains
> +- power-domain-names: Must be "pcie", "pcie_phy", "hsio_gpio"
> +- clock-names: Must include the following additional entries:
> > +	- "pcie_per"
> +- hsio-cfg: hsio configration mode when the pcie node is supported.
> +ÂÂ1: pciea 2 lanes and one sata ahci port.
> +ÂÂ2: pciea 1 lane, pcieb 1 lane and one sata ahci port.
> +ÂÂ3: pciea 2 lanes, pcieb 1 lane.
> +- local-addr: the local address used in hsio module on i.MX8QM/QXP.
> > +	Example:
> > +		hsio-cfg = <2>;
> > +		local-addr = <0x80000000>;
> +
> ÂExample:
> Â
> > Â	pcie@01000000 {