Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset

From: Maxime Ripard
Date: Thu Mar 14 2019 - 11:46:33 EST

On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote:
> The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
> Fix this problem.
> Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
> Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx>

Applied, thanks!

Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering

Attachment: signature.asc
Description: PGP signature