[PATCH 07/12] misc: xilinx_sdfec: Add ability to configure LDPC

[Dragan Cvetic]

Add the capability to configure LDPC mode via the ioctl
XSDFEC_ADD_LDPC_CODE_PARAMS. The ioctl set the parameters
and tables for the LDPC FEC algorithm.

Reviewed-by: Michal Simek <michal.simek@xxxxxxxxxx>
Tested-by: Dragan Cvetic <dragan.cvetic@xxxxxxxxxx>
Signed-off-by: Derek Kiernan <derek.kiernan@xxxxxxxxxx>
Signed-off-by: Dragan Cvetic <dragan.cvetic@xxxxxxxxxx>
---
 drivers/misc/xilinx_sdfec.c      | 345 +++++++++++++++++++++++++++++++++++++++
 include/uapi/misc/xilinx_sdfec.h | 114 +++++++++++++
 2 files changed, 459 insertions(+)

diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c
index 58b1c57..088ad9d 100644
--- a/drivers/misc/xilinx_sdfec.c
+++ b/drivers/misc/xilinx_sdfec.c
@@ -121,6 +121,58 @@ static dev_t xsdfec_devt;
 #define XSDFEC_TURBO_SCALE_BIT_POS (8)
 #define XSDFEC_TURBO_SCALE_MAX (15)

+/* REG0 Register */
+#define XSDFEC_LDPC_CODE_REG0_ADDR_BASE (0x2000)
+#define XSDFEC_LDPC_CODE_REG0_ADDR_HIGH (0x27F0)
+#define XSDFEC_REG0_N_MIN (4)
+#define XSDFEC_REG0_N_MAX (32768)
+#define XSDFEC_REG0_N_MUL_P (256)
+#define XSDFEC_REG0_N_LSB (0)
+#define XSDFEC_REG0_K_MIN (2)
+#define XSDFEC_REG0_K_MAX (32766)
+#define XSDFEC_REG0_K_MUL_P (256)
+#define XSDFEC_REG0_K_LSB (16)
+
+/* REG1 Register */
+#define XSDFEC_LDPC_CODE_REG1_ADDR_BASE (0x2004)
+#define XSDFEC_LDPC_CODE_REG1_ADDR_HIGH (0x27f4)
+#define XSDFEC_REG1_PSIZE_MIN (2)
+#define XSDFEC_REG1_PSIZE_MAX (512)
+#define XSDFEC_REG1_NO_PACKING_MASK (0x400)
+#define XSDFEC_REG1_NO_PACKING_LSB (10)
+#define XSDFEC_REG1_NM_MASK (0xFF800)
+#define XSDFEC_REG1_NM_LSB (11)
+#define XSDFEC_REG1_BYPASS_MASK (0x100000)
+
+/* REG2 Register */
+#define XSDFEC_LDPC_CODE_REG2_ADDR_BASE (0x2008)
+#define XSDFEC_LDPC_CODE_REG2_ADDR_HIGH (0x27f8)
+#define XSDFEC_REG2_NLAYERS_MIN (1)
+#define XSDFEC_REG2_NLAYERS_MAX (256)
+#define XSDFEC_REG2_NNMQC_MASK (0xFFE00)
+#define XSDFEC_REG2_NMQC_LSB (9)
+#define XSDFEC_REG2_NORM_TYPE_MASK (0x100000)
+#define XSDFEC_REG2_NORM_TYPE_LSB (20)
+#define XSDFEC_REG2_SPECIAL_QC_MASK (0x200000)
+#define XSDFEC_REG2_SPEICAL_QC_LSB (21)
+#define XSDFEC_REG2_NO_FINAL_PARITY_MASK (0x400000)
+#define XSDFEC_REG2_NO_FINAL_PARITY_LSB (22)
+#define XSDFEC_REG2_MAX_SCHEDULE_MASK (0x1800000)
+#define XSDFEC_REG2_MAX_SCHEDULE_LSB (23)
+
+/* REG3 Register */
+#define XSDFEC_LDPC_CODE_REG3_ADDR_BASE (0x200C)
+#define XSDFEC_LDPC_CODE_REG3_ADDR_HIGH (0x27FC)
+#define XSDFEC_REG3_LA_OFF_LSB (8)
+#define XSDFEC_REG3_QC_OFF_LSB (16)
+
+#define XSDFEC_LDPC_REG_JUMP (0x10)
+#define XSDFEC_REG_WIDTH_JUMP (4)
+
+#define XSDFEC_SC_TABLE_DEPTH (0x3FC)
+#define XSDFEC_LA_TABLE_DEPTH (0xFFC)
+#define XSDFEC_QC_TABLE_DEPTH (0x7FFC)
+
 /**
  * struct xsdfec_clks - For managing SD-FEC clocks
  * @core_clk: Main processing clock for core
@@ -328,6 +380,296 @@ static int xsdfec_get_turbo(struct xsdfec_dev *xsdfec, void __user *arg)
        return err;
 }

+static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize,
+                            u32 offset)
+{
+       u32 wdata;
+
+       if (n < XSDFEC_REG0_N_MIN || n > XSDFEC_REG0_N_MAX ||
+           (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) {
+               dev_err(xsdfec->dev, "N value is not in range");
+               return -EINVAL;
+       }
+       n <<= XSDFEC_REG0_N_LSB;
+
+       if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX ||
+           (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) {
+               dev_err(xsdfec->dev, "K value is not in range");
+               return -EINVAL;
+       }
+       k = k << XSDFEC_REG0_K_LSB;
+       wdata = k | n;
+
+       if (XSDFEC_LDPC_CODE_REG0_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
+           XSDFEC_LDPC_CODE_REG0_ADDR_HIGH) {
+               dev_err(xsdfec->dev, "Writing outside of LDPC reg0 space 0x%x",
+                       XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP));
+               return -EINVAL;
+       }
+       xsdfec_regwrite(xsdfec,
+                       XSDFEC_LDPC_CODE_REG0_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP),
+                       wdata);
+       return 0;
+}
+
+static int xsdfec_reg1_write(struct xsdfec_dev *xsdfec, u32 psize,
+                            u32 no_packing, u32 nm, u32 offset)
+{
+       u32 wdata;
+
+       if (psize < XSDFEC_REG1_PSIZE_MIN || psize > XSDFEC_REG1_PSIZE_MAX) {
+               dev_err(xsdfec->dev, "Psize is not in range");
+               return -EINVAL;
+       }
+
+       if (no_packing != 0 && no_packing != 1)
+               dev_err(xsdfec->dev, "No-packing bit register invalid");
+       no_packing = ((no_packing << XSDFEC_REG1_NO_PACKING_LSB) &
+                     XSDFEC_REG1_NO_PACKING_MASK);
+
+       if (nm & ~(XSDFEC_REG1_NM_MASK >> XSDFEC_REG1_NM_LSB))
+               dev_err(xsdfec->dev, "NM is beyond 10 bits");
+       nm = (nm << XSDFEC_REG1_NM_LSB) & XSDFEC_REG1_NM_MASK;
+
+       wdata = nm | no_packing | psize;
+       if (XSDFEC_LDPC_CODE_REG1_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
+           XSDFEC_LDPC_CODE_REG1_ADDR_HIGH) {
+               dev_err(xsdfec->dev, "Writing outside of LDPC reg1 space 0x%x",
+                       XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP));
+               return -EINVAL;
+       }
+       xsdfec_regwrite(xsdfec,
+                       XSDFEC_LDPC_CODE_REG1_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP),
+                       wdata);
+       return 0;
+}
+
+static int xsdfec_reg2_write(struct xsdfec_dev *xsdfec, u32 nlayers, u32 nmqc,
+                            u32 norm_type, u32 special_qc, u32 no_final_parity,
+                            u32 max_schedule, u32 offset)
+{
+       u32 wdata;
+
+       if (nlayers < XSDFEC_REG2_NLAYERS_MIN ||
+           nlayers > XSDFEC_REG2_NLAYERS_MAX) {
+               dev_err(xsdfec->dev, "Nlayers is not in range");
+               return -EINVAL;
+       }
+
+       if (nmqc & ~(XSDFEC_REG2_NNMQC_MASK >> XSDFEC_REG2_NMQC_LSB))
+               dev_err(xsdfec->dev, "NMQC exceeds 11 bits");
+       nmqc = (nmqc << XSDFEC_REG2_NMQC_LSB) & XSDFEC_REG2_NNMQC_MASK;
+
+       if (norm_type > 1)
+               dev_err(xsdfec->dev, "Norm type is invalid");
+       norm_type = ((norm_type << XSDFEC_REG2_NORM_TYPE_LSB) &
+                    XSDFEC_REG2_NORM_TYPE_MASK);
+       if (special_qc > 1)
+               dev_err(xsdfec->dev, "Special QC in invalid");
+       special_qc = ((special_qc << XSDFEC_REG2_SPEICAL_QC_LSB) &
+                     XSDFEC_REG2_SPECIAL_QC_MASK);
+
+       if (no_final_parity > 1)
+               dev_err(xsdfec->dev, "No final parity check invalid");
+       no_final_parity =
+               ((no_final_parity << XSDFEC_REG2_NO_FINAL_PARITY_LSB) &
+                XSDFEC_REG2_NO_FINAL_PARITY_MASK);
+       if (max_schedule &
+           ~(XSDFEC_REG2_MAX_SCHEDULE_MASK >> XSDFEC_REG2_MAX_SCHEDULE_LSB))
+               dev_err(xsdfec->dev, "Max Schdule exceeds 2 bits");
+       max_schedule = ((max_schedule << XSDFEC_REG2_MAX_SCHEDULE_LSB) &
+                       XSDFEC_REG2_MAX_SCHEDULE_MASK);
+
+       wdata = (max_schedule | no_final_parity | special_qc | norm_type |
+                nmqc | nlayers);
+
+       if (XSDFEC_LDPC_CODE_REG2_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
+           XSDFEC_LDPC_CODE_REG2_ADDR_HIGH) {
+               dev_err(xsdfec->dev, "Writing outside of LDPC reg2 space 0x%x",
+                       XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP));
+               return -EINVAL;
+       }
+       xsdfec_regwrite(xsdfec,
+                       XSDFEC_LDPC_CODE_REG2_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP),
+                       wdata);
+       return 0;
+}
+
+static int xsdfec_reg3_write(struct xsdfec_dev *xsdfec, u8 sc_off, u8 la_off,
+                            u16 qc_off, u32 offset)
+{
+       u32 wdata;
+
+       wdata = ((qc_off << XSDFEC_REG3_QC_OFF_LSB) |
+                (la_off << XSDFEC_REG3_LA_OFF_LSB) | sc_off);
+       if (XSDFEC_LDPC_CODE_REG3_ADDR_BASE + (offset * XSDFEC_LDPC_REG_JUMP) >
+           XSDFEC_LDPC_CODE_REG3_ADDR_HIGH) {
+               dev_err(xsdfec->dev, "Writing outside of LDPC reg3 space 0x%x",
+                       XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP));
+               return -EINVAL;
+       }
+       xsdfec_regwrite(xsdfec,
+                       XSDFEC_LDPC_CODE_REG3_ADDR_BASE +
+                               (offset * XSDFEC_LDPC_REG_JUMP),
+                       wdata);
+       return 0;
+}
+
+static int xsdfec_sc_table_write(struct xsdfec_dev *xsdfec, u32 offset,
+                                u32 *sc_ptr, u32 len)
+{
+       u32 reg;
+
+       /*
+        * Writes that go beyond the length of
+        * Shared Scale(SC) table should fail
+        */
+       if ((XSDFEC_REG_WIDTH_JUMP * (offset + len)) > XSDFEC_SC_TABLE_DEPTH) {
+               dev_err(xsdfec->dev, "Write exceeds SC table length");
+               return -EINVAL;
+       }
+
+       for (reg = 0; reg < len; reg++) {
+               xsdfec_regwrite(xsdfec,
+                               XSDFEC_LDPC_SC_TABLE_ADDR_BASE +
+                                       (offset + reg) * XSDFEC_REG_WIDTH_JUMP,
+                               sc_ptr[reg]);
+       }
+       return reg;
+}
+
+static int xsdfec_la_table_write(struct xsdfec_dev *xsdfec, u32 offset,
+                                u32 *la_ptr, u32 len)
+{
+       u32 reg;
+
+       if (XSDFEC_REG_WIDTH_JUMP * (offset + len) > XSDFEC_LA_TABLE_DEPTH) {
+               dev_err(xsdfec->dev, "Write exceeds LA table length");
+               return -EINVAL;
+       }
+
+       for (reg = 0; reg < len; reg++) {
+               xsdfec_regwrite(xsdfec,
+                               XSDFEC_LDPC_LA_TABLE_ADDR_BASE +
+                                       (offset + reg) * XSDFEC_REG_WIDTH_JUMP,
+                               la_ptr[reg]);
+       }
+       return reg;
+}
+
+static int xsdfec_qc_table_write(struct xsdfec_dev *xsdfec, u32 offset,
+                                u32 *qc_ptr, u32 len)
+{
+       u32 reg;
+
+       if (XSDFEC_REG_WIDTH_JUMP * (offset + len) > XSDFEC_QC_TABLE_DEPTH) {
+               dev_err(xsdfec->dev, "Write exceeds QC table length");
+               return -EINVAL;
+       }
+
+       for (reg = 0; reg < len; reg++) {
+               xsdfec_regwrite(xsdfec,
+                               XSDFEC_LDPC_QC_TABLE_ADDR_BASE +
+                                       (offset + reg) * XSDFEC_REG_WIDTH_JUMP,
+                               qc_ptr[reg]);
+       }
+
+       return reg;
+}
+
+static int xsdfec_add_ldpc(struct xsdfec_dev *xsdfec, void __user *arg)
+{
+       struct xsdfec_ldpc_params *ldpc;
+       int ret;
+
+       ldpc = kzalloc(sizeof(*ldpc), GFP_KERNEL);
+       if (!ldpc)
+               return -ENOMEM;
+
+       ret = copy_from_user(ldpc, arg, sizeof(*ldpc));
+       if (ret) {
+               dev_err(xsdfec->dev, "%s failed to copy from user for SDFEC%d",
+                       __func__, xsdfec->config.fec_id);
+               goto err_out;
+       }
+       if (xsdfec->config.code == XSDFEC_TURBO_CODE) {
+               dev_err(xsdfec->dev,
+                       "%s: Unable to write LDPC to SDFEC%d check DT",
+                       __func__, xsdfec->config.fec_id);
+               ret = -EIO;
+               goto err_out;
+       }
+
+       /* Verify Device has not started */
+       if (xsdfec->state == XSDFEC_STARTED) {
+               dev_err(xsdfec->dev,
+                       "%s attempting to write LDPC code while started for SDFEC%d",
+                       __func__, xsdfec->config.fec_id);
+               ret = -EIO;
+               goto err_out;
+       }
+
+       if (xsdfec->config.code_wr_protect) {
+               dev_err(xsdfec->dev,
+                       "%s writing LDPC code while Code Write Protection enabled for SDFEC%d",
+                       __func__, xsdfec->config.fec_id);
+               ret = -EIO;
+               goto err_out;
+       }
+
+       /* Write Reg 0 */
+       ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize,
+                               ldpc->code_id);
+       if (ret)
+               goto err_out;
+
+       /* Write Reg 1 */
+       ret = xsdfec_reg1_write(xsdfec, ldpc->psize, ldpc->no_packing, ldpc->nm,
+                               ldpc->code_id);
+       if (ret)
+               goto err_out;
+
+       /* Write Reg 2 */
+       ret = xsdfec_reg2_write(xsdfec, ldpc->nlayers, ldpc->nmqc,
+                               ldpc->norm_type, ldpc->special_qc,
+                               ldpc->no_final_parity, ldpc->max_schedule,
+                               ldpc->code_id);
+       if (ret)
+               goto err_out;
+
+       /* Write Reg 3 */
+       ret = xsdfec_reg3_write(xsdfec, ldpc->sc_off, ldpc->la_off,
+                               ldpc->qc_off, ldpc->code_id);
+       if (ret)
+               goto err_out;
+
+       /* Write Shared Codes */
+       ret = xsdfec_sc_table_write(xsdfec, ldpc->sc_off, ldpc->sc_table,
+                                   ldpc->nlayers);
+       if (ret < 0)
+               goto err_out;
+
+       ret = xsdfec_la_table_write(xsdfec, 4 * ldpc->la_off, ldpc->la_table,
+                                   ldpc->nlayers);
+       if (ret < 0)
+               goto err_out;
+
+       ret = xsdfec_qc_table_write(xsdfec, 4 * ldpc->qc_off, ldpc->qc_table,
+                                   ldpc->nqc);
+       if (ret > 0)
+               ret = 0;
+err_out:
+       kfree(ldpc);
+       return ret;
+}
+
 static u32
 xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg)
 {
@@ -435,6 +777,9 @@ static long xsdfec_dev_ioctl(struct file *fptr, unsigned int cmd,
        case XSDFEC_GET_TURBO:
                rval = xsdfec_get_turbo(xsdfec, arg);
                break;
+       case XSDFEC_ADD_LDPC_CODE_PARAMS:
+               rval = xsdfec_add_ldpc(xsdfec, arg);
+               break;
        default:
                /* Should not get here */
                dev_err(xsdfec->dev, "Undefined SDFEC IOCTL");
diff --git a/include/uapi/misc/xilinx_sdfec.h b/include/uapi/misc/xilinx_sdfec.h
index 1a15771..b70dbff 100644
--- a/include/uapi/misc/xilinx_sdfec.h
+++ b/include/uapi/misc/xilinx_sdfec.h
@@ -11,6 +11,14 @@
 #ifndef __XILINX_SDFEC_H__
 #define __XILINX_SDFEC_H__

+/* Shared LDPC Tables */
+#define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
+#define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC)
+#define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
+#define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC)
+#define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
+#define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC)
+
 /**
  * enum xsdfec_code - Code Type.
  * @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode.
@@ -125,6 +133,56 @@ struct xsdfec_turbo {
 };

 /**
+ * struct xsdfec_ldpc_params - User data for LDPC codes.
+ * @n: Number of code word bits
+ * @k: Number of information bits
+ * @psize: Size of sub-matrix
+ * @nlayers: Number of layers in code
+ * @nqc: Quasi Cyclic Number
+ * @nmqc: Number of M-sized QC operations in parity check matrix
+ * @nm: Number of M-size vectors in N
+ * @norm_type: Normalization required or not
+ * @no_packing: Determines if multiple QC ops should be performed
+ * @special_qc: Sub-Matrix property for Circulant weight > 0
+ * @no_final_parity: Decide if final parity check needs to be performed
+ * @max_schedule: Experimental code word scheduling limit
+ * @sc_off: SC offset
+ * @la_off: LA offset
+ * @qc_off: QC offset
+ * @sc_table: SC Table
+ * @la_table: LA Table
+ * @qc_table: QC Table
+ * @code_id: LDPC Code
+ *
+ * This structure describes the LDPC code that is passed to the driver by the
+ * application.
+ */
+struct xsdfec_ldpc_params {
+       u32 n;
+       u32 k;
+       u32 psize;
+       u32 nlayers;
+       u32 nqc;
+       u32 nmqc;
+       u32 nm;
+       u32 norm_type;
+       u32 no_packing;
+       u32 special_qc;
+       u32 no_final_parity;
+       u32 max_schedule;
+       u32 sc_off;
+       u32 la_off;
+       u32 qc_off;
+       u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH -
+                    XSDFEC_LDPC_SC_TABLE_ADDR_BASE];
+       u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH -
+                    XSDFEC_LDPC_LA_TABLE_ADDR_BASE];
+       u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH -
+                    XSDFEC_LDPC_QC_TABLE_ADDR_BASE];
+       u16 code_id;
+};
+
+/**
  * struct xsdfec_status - Status of SD-FEC core.
  * @fec_id: ID of SD-FEC instance. ID is limited to the number of active
  *          SD-FEC's in the FPGA and is related to the driver instance
@@ -176,6 +234,41 @@ struct xsdfec_config {
        struct xsdfec_irq irq;
 };

+/**
+ * struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table
+ *                                       entries for an individual LPDC code
+ *                                       parameter.
+ * @sc_size: Size of SC table used
+ * @la_size: Size of LA table used
+ * @qc_size: Size of QC table used
+ */
+struct xsdfec_ldpc_param_table_sizes {
+       u32 sc_size;
+       u32 la_size;
+       u32 qc_size;
+};
+
+/**
+ * xsdfec_calculate_shared_ldpc_table_entry_size - Calculates shared code
+ * table sizes.
+ * @ldpc: Pointer to the LPDC Code Parameters
+ * @table_sizes: Pointer to structure containing the calculated table sizes
+ *
+ * Calculates the size of shared LDPC code tables used for a specified LPDC code
+ * parameters.
+ */
+inline void
+xsdfec_calculate_shared_ldpc_table_entry_size(struct xsdfec_ldpc_params *ldpc,
+       struct xsdfec_ldpc_param_table_sizes *table_sizes)
+{
+       /* Calculate the sc_size in 32 bit words */
+       table_sizes->sc_size = (ldpc->nlayers + 3) >> 2;
+       /* Calculate the la_size in 256 bit words */
+       table_sizes->la_size = ((ldpc->nlayers << 2) + 15) >> 4;
+       /* Calculate the qc_size in 256 bit words */
+       table_sizes->qc_size = ((ldpc->nqc << 2) + 15) >> 4;
+}
+
 /*
  * XSDFEC IOCTL List
  */
@@ -196,6 +289,27 @@ struct xsdfec_config {
  */
 #define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo *)
 /**
+ * DOC: XSDFEC_ADD_LDPC_CODE_PARAMS
+ * @Parameters
+ *
+ * @struct xsdfec_ldpc_params *
+ *     Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code
+ *     parameters to be added to the SD-FEC Block
+ *
+ * @Description
+ * ioctl to add an LDPC code to the SD-FEC LDPC codes
+ *
+ * This can only be used when:
+ *
+ * - Driver is in the XSDFEC_STOPPED state
+ *
+ * - SD-FEC core is configured as LPDC
+ *
+ * - SD-FEC Code Write Protection is disabled
+ */
+#define XSDFEC_ADD_LDPC_CODE_PARAMS                                            \
+       _IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params *)
+/**
  * DOC: XSDFEC_GET_TURBO
  * @Parameters
  *
--
2.7.4

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