Re: [PATCH 03/22] perf/x86/intel: Support adaptive PEBSv4

[Peter Zijlstra]

On Tue, Mar 19, 2019 at 09:03:37AM -0700, Andi Kleen wrote:
> On Tue, Mar 19, 2019 at 03:47:48PM +0100, Peter Zijlstra wrote:
> > On Mon, Mar 18, 2019 at 02:41:25PM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> > > From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> > > 
> > > Adaptive PEBS is a new way to report PEBS sampling information. Instead
> > > of a fixed size record for all PEBS events it allows to configure the
> > > PEBS record to only include the information needed. Events can then opt
> > > in to use such an extended record, or stay with a basic record which
> > > only contains the IP.
> > > 
> > > The major new feature is to support LBRs in PEBS record.
> > > This allows (much faster) large PEBS, while still supporting callstacks
> > > through callstack LBR. 
> > 
> > Does it also allow normal LBR usage? Or does it have to be callstacks?
> 
> It allows normal LBR too. But I would expect callstack to be the most
> common one.  As long as you set a period you can get multi-record
> PEBS with -g, which has a lot lower lower overhead than using
> PMIs.
> 
> Eventually I hope we can even make multi-record PEBS
> work in frequency mode by averaging the frequency over multiple
> records.

Should be doable..

> > >  	hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
> > > +	hwc->config &= ~ICL_EVENTSEL_ADAPTIVE;
> > 
> > Just curious; the way I read the SDM, we could leave this set, is that
> > correct?
> 
> It needs to be cleared to get the basic record (which should be
> a common case)

But you unconditionally set the bit when you enable PEBS for the event.
So why clear it?