Re: [PATCH net-next 1/2] net: phy: Prepare for moving Omega out of bcm7xxx

[Scott Branden]

Looks good.

On 2019-03-20 12:53 p.m., Florian Fainelli wrote:
> The Omega PHY entry was added to bcm7xxx.c out of convenience and this
> breaks the one driver per product line paradigm that was applied up
> until now. Since the AFE initialization is shared between Omega and
> BCM7xxx move the relevant functions to bcm-phy-lib.[ch]. No functional
> changes introduced.
>
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
Reviewed-by: Scott Branden <scott.branden@xxxxxxxxxxxx>
> ---
>   drivers/net/phy/bcm-phy-lib.c | 52 ++++++++++++++++++++++++
>   drivers/net/phy/bcm-phy-lib.h | 20 ++++++++++
>   drivers/net/phy/bcm7xxx.c     | 75 ++---------------------------------
>   3 files changed, 76 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/net/phy/bcm-phy-lib.c b/drivers/net/phy/bcm-phy-lib.c
> index a75642051b8b..e0d3310957ff 100644
> --- a/drivers/net/phy/bcm-phy-lib.c
> +++ b/drivers/net/phy/bcm-phy-lib.c
> @@ -371,6 +371,58 @@ void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
>   }
>   EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
>   
> +void bcm_phy_r_rc_cal_reset(struct phy_device *phydev)
> +{
> +	/* Reset R_CAL/RC_CAL Engine */
> +	bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
> +
> +	/* Disable Reset R_AL/RC_CAL Engine */
> +	bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
> +}
> +EXPORT_SYMBOL_GPL(bcm_phy_r_rc_cal_reset);
> +
> +int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev)
> +{
> +	/* Increase VCO range to prevent unlocking problem of PLL at low
> +	 * temp
> +	 */
> +	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
> +
> +	/* Change Ki to 011 */
> +	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
> +
> +	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
> +	 * to 111
> +	 */
> +	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
> +
> +	/* Adjust bias current trim by -3 */
> +	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
> +
> +	/* Switch to CORE_BASE1E */
> +	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
> +
> +	bcm_phy_r_rc_cal_reset(phydev);
> +
> +	/* write AFE_RXCONFIG_0 */
> +	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
> +
> +	/* write AFE_RXCONFIG_1 */
> +	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
> +
> +	/* write AFE_RX_LP_COUNTER */
> +	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
> +
> +	/* write AFE_HPF_TRIM_OTHERS */
> +	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
> +
> +	/* write AFTE_TX_CONFIG */
> +	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(bcm_phy_28nm_a0b0_afe_config_init);
> +
>   MODULE_DESCRIPTION("Broadcom PHY Library");
>   MODULE_LICENSE("GPL v2");
>   MODULE_AUTHOR("Broadcom Corporation");
> diff --git a/drivers/net/phy/bcm-phy-lib.h b/drivers/net/phy/bcm-phy-lib.h
> index 17faaefcfd60..5ecacb4e64f0 100644
> --- a/drivers/net/phy/bcm-phy-lib.h
> +++ b/drivers/net/phy/bcm-phy-lib.h
> @@ -9,6 +9,24 @@
>   #include <linux/brcmphy.h>
>   #include <linux/phy.h>
>   
> +/* 28nm only register definitions */
> +#define MISC_ADDR(base, channel)	base, channel
> +
> +#define DSP_TAP10			MISC_ADDR(0x0a, 0)
> +#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
> +#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
> +#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)
> +
> +#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
> +#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
> +#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
> +#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
> +#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
> +#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
> +#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
> +#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)
> +
> +
>   int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
>   int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
>   
> @@ -45,5 +63,7 @@ int bcm_phy_get_sset_count(struct phy_device *phydev);
>   void bcm_phy_get_strings(struct phy_device *phydev, u8 *data);
>   void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
>   		       struct ethtool_stats *stats, u64 *data);
> +void bcm_phy_r_rc_cal_reset(struct phy_device *phydev);
> +int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev);
>   
>   #endif /* _LINUX_BCM_PHY_LIB_H */
> diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
> index b8415f8fae14..dddeffa23aa1 100644
> --- a/drivers/net/phy/bcm7xxx.c
> +++ b/drivers/net/phy/bcm7xxx.c
> @@ -37,77 +37,10 @@
>   #define MII_BCM7XXX_SHD_3_TL4		0x23
>   #define  MII_BCM7XXX_TL4_RST_MSK	(BIT(2) | BIT(1))
>   
> -/* 28nm only register definitions */
> -#define MISC_ADDR(base, channel)	base, channel
> -
> -#define DSP_TAP10			MISC_ADDR(0x0a, 0)
> -#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
> -#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
> -#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)
> -
> -#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
> -#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
> -#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
> -#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
> -#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
> -#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
> -#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
> -#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)
> -
>   struct bcm7xxx_phy_priv {
>   	u64	*stats;
>   };
>   
> -static void r_rc_cal_reset(struct phy_device *phydev)
> -{
> -	/* Reset R_CAL/RC_CAL Engine */
> -	bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010);
> -
> -	/* Disable Reset R_AL/RC_CAL Engine */
> -	bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000);
> -}
> -
> -static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
> -{
> -	/* Increase VCO range to prevent unlocking problem of PLL at low
> -	 * temp
> -	 */
> -	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
> -
> -	/* Change Ki to 011 */
> -	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
> -
> -	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
> -	 * to 111
> -	 */
> -	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
> -
> -	/* Adjust bias current trim by -3 */
> -	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
> -
> -	/* Switch to CORE_BASE1E */
> -	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
> -
> -	r_rc_cal_reset(phydev);
> -
> -	/* write AFE_RXCONFIG_0 */
> -	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
> -
> -	/* write AFE_RXCONFIG_1 */
> -	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
> -
> -	/* write AFE_RX_LP_COUNTER */
> -	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
> -
> -	/* write AFE_HPF_TRIM_OTHERS */
> -	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
> -
> -	/* write AFTE_TX_CONFIG */
> -	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
> -
> -	return 0;
> -}
> -
>   static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
>   {
>   	/* AFE_RXCONFIG_0 */
> @@ -143,7 +76,7 @@ static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
>   	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
>   
>   	/* Reset R_CAL/RC_CAL engine */
> -	r_rc_cal_reset(phydev);
> +	bcm_phy_r_rc_cal_reset(phydev);
>   
>   	return 0;
>   }
> @@ -171,7 +104,7 @@ static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
>   	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
>   
>   	/* Reset R_CAL/RC_CAL engine */
> -	r_rc_cal_reset(phydev);
> +	bcm_phy_r_rc_cal_reset(phydev);
>   
>   	return 0;
>   }
> @@ -196,7 +129,7 @@ static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
>   	/* Enable ffe zero detection for Vitesse interoperability */
>   	bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
>   
> -	r_rc_cal_reset(phydev);
> +	bcm_phy_r_rc_cal_reset(phydev);
>   
>   	return 0;
>   }
> @@ -227,7 +160,7 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
>   	switch (rev) {
>   	case 0xa0:
>   	case 0xb0:
> -		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
> +		ret = bcm_phy_28nm_a0b0_afe_config_init(phydev);
>   		break;
>   	case 0xd0:
>   		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);