Re: [RFC PATCH v2 1/5] mtd: cfi_cmdset_0002: Add support for polling status register

[Joakim Tjernlund]

On Mon, 2019-03-25 at 18:27 +0530, Vignesh Raghavendra wrote:
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> 
> Hi,
> 
> On 21/03/19 11:41 PM, Joakim Tjernlund wrote:
> > On Thu, 2019-03-21 at 23:15 +0530, Vignesh Raghavendra wrote:
> > > HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command
> > > Set(0x0002) for flash operations, therefore drivers/mtd/chips/cfi_cmdset_0002.c
> > > can be use as is. But these devices do not support DQ polling method of
> > > determining chip ready/good status. These flashes provide Status
> > > Register whose bits can be polled to know status of flash operation.
> > > 
> > > Cypress HyperFlash datasheet here[1], talks about CFI Amd/Fujitsu
> > > Extended Query version 1.5. Bit 0 of "Software Features supported" field
> > > of CFI Primary Vendor-Specific Extended Query table indicates
> > > presence/absence of status register and Bit 1 indicates whether or not
> > > DQ polling is supported. Using these bits, its possible to determine
> > > whether flash supports DQ polling or need to use Status Register.
> > > 
> > > Add support for polling status register to know device ready/status of
> > > erase/write operations when DQ polling is not supported.
> > 
> > Isn't this new Status scheme just a copy of Intels(cmdset_0001)?
> 
> Yes, but with one difference: At the end of program/erase operation,
> device directly enters status register mode and  starts reflecting
> status register content at any address.
> The device remains in the read status register state until another
> command is written to the device. Therefore there is notion of device is
> in "status register read mode" (FL_STATUS) state

That seems to vary and long time ago RMK added this:
		/* If the flash has finished erasing, then 'erase suspend'
		 * appears to make some (28F320) flash devices switch to
		 * 'read' mode.  Make sure that we switch to 'read status'
		 * mode so we get the right data. --rmk
		 */
		map_write(map, CMD(0x70), chip->in_progress_block_addr);

> 
> But in case of cfi_cmdset_0002, once program/erase operation is
> complete, device returns to previous address space overlay from which
> operation was started from (mostly read mode)

I hope you can do the same as Intel here, issue an explicit Status CMD or you will be in trouble.

Also, I think you need to use the various map_word_xxx as in:
status = map_read(map, chip->in_progress_block_addr);
if (map_word_andequal(map, status, status_OK, status_OK))
	break;
otherwise you will break interleaved setups(like two 8-bit flashes in parallel to
form one 16 bit bus). Maybe this is not supported for CMDSET 0002 ?

 Jocke

> 
> In order to enter status register overlay mode, Read Status command is
> to be written to addr_unlock1(0x555) address. The overlay is in effect
> for one read access, specifically the next read access that follows the
> Status Register Read command
> Therefore code around FL_STATUS state in cfi_cmdset_0001 is not
> applicable to cfi_cmdset_0002 as is.
> 
> 
> > If so I think the new status impl. in 0002 should borrow from 0001 as this is a
> > hardened and battle tested impl.
> > 
> 
> In case of cfi_cmdset_0001.c, program/erase is followed by
> inval_cache_and_wait_for_operation() to poll ready bit and based on
> status register value, success or the error handling is done.
> 
> Most of the code corresponding to inval_cache_and_wait_for_operation()
> is already in cfi_cmdset_0002.c. So, whats missing in this patch is
> handling and reporting of errors as reflected in status register after
> write/erase failures. I will add that in the next version.
> 
> But, I don't see much to borrow apart from error handling sequence.
> Please, let me know if I missed something.
> 
> > I know other modern 0002 chips supports both old and new impl. of Status and I world
> > guess that we will see more chips with new Status only.
> > 
> 
> Agreed. Newer devices would mostly be CFI 1.5.
> 
> --
> Regards
> Vignesh