Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

[Alan Tull]

On Mon, Mar 25, 2019 at 7:44 PM Wu Hao <hao.wu@xxxxxxxxx> wrote:
>
> On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote:
> > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao <hao.wu@xxxxxxxxx> wrote:
> >
> > Hi Hao,
> >
> > Looks good, one question below.
> >
> > >
> > > Current driver checks if input bitstream file size is aligned or
> > > not per PR data width (default 32bits). It requires one additional
> > > step for end user when they generate the bitstream file, padding
> > > extra zeros to bitstream file to align its size per PR data width,
> > > but they don't have to as hardware will drop extra padding bytes
> > > automatically.
> > >
> > > In order to simplify the user steps, this patch aligns PR buffer
> > > size per PR data width in driver, to allow user to pass unaligned
> > > size bitstream files to driver.
> > >
> > > Signed-off-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> > > Signed-off-by: Wu Hao <hao.wu@xxxxxxxxx>

Acked-by: Alan Tull <atull@xxxxxxxxxx>

Thanks,
Alan