Re: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake

[You-Sheng Yang]

On 2019/4/8 8:03 PM, Thomas Gleixner wrote:
> On Mon, 8 Apr 2019, You-Sheng Yang wrote:
> 
>> From: You-Sheng Yang <vicamo.yang@xxxxxxxxxxxxx>
>>
>> On Intel CoffeeLake it's observed tsc is always marked unstable
>> unexpectedly after entering idle state Package C10(PC10), and then clock
>> source is switched to hpet. This patch marks tsc as reliable when CPUID
>> matches CoffeeLake.
> 
> This lacks a proper analysis:
> 
>   1) Why is it marked unstable

Usually the differences between wd_nsec and cs_nsec in function
clocksource_watchdog in kernel/time/clocksource.c would be less than a
few thousand nanoseconds. However, when CPU is entering deeper idle
state, PC10, the hpet clocksource readings starts to give inaccurate
values for unknown reason, and the differences to cs_nsec varies from a
few hundred nanoseconds to several hundred millisecond, which is larger
than WATCHDOG_THRESHOLD (62.5ms) and finally results in tsc being marked
unreliable. No HPET overflow is found when this occurs.

>   2) Why is it correct to set that for coffeelake

So far this strange behaviour is only found on coffeelake. Besides this,
no much I can tell actually. This could be probably wrong, but may serve
as a start to bring up some more discussion/investigation to solve the
problem. I would be more than willing to help verifying further
appropriate fixes.

Thank you.

You-Sheng Yang