sorry to push for an answer but I do not want to take the risk of designing
something useless. I do not know how should I interpret a no-answer.
If the solution really does not exist today, then I would like to collect
opinions/arguments/requirements on the topic so that I can write something
useful not only for CERN but for the entire community.
On Wednesday, March 27, 2019 6:17:18 PM CEST Federico Vaga wrote:
I'm looking for guidance
What I have:
* Intel x86_64 computer
* PCIe card with FPGA on it
What I want to achieve:
* load an FPGA bitstream on the card
* load a device-tree like description for the FPGA devices contained in the
This is achievable on ARM with DeviceTree, overlay-dt, fpga-mgr; but I'm
puzzled about the x86_64 use-case. I'm not able to find recent and clear
Does anyone know if this is doable? Perhaps with ACPI SSDTs overlay? Or with