Re: [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support

[Peter Zijlstra]

On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> +static struct event_constraint *
> +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> +			  struct perf_event *event)

That 'tnt' still cracks me up, I keep seeing explosions.

> +{
> +	struct event_constraint *c;
> +
> +	/*
> +	 * :ppp means to do reduced skid PEBS,
> +	 * which is available on PMC0 and fixed counter 0.
> +	 */
> +	if (event->attr.precise_ip == 3) {
> +		/* Force instruction:ppp on PMC0 and Fixed counter 0 */
> +		if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))
> +			return &fixed0_counter0_constraint;
> +
> +		return &counter0_constraint;
> +	}
> +
> +	c = intel_get_event_constraints(cpuc, idx, event);
> +
> +	return c;
> +}

I changed that like so:

--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_
 	 */
 	if (event->attr.precise_ip == 3) {
 		/* Force instruction:ppp on PMC0 and Fixed counter 0 */
-		if (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0))
+		if (constraint_match(&fixed_counter0_constraint, event->hw.config))
 			return &fixed0_counter0_constraint;
 
 		return &counter0_constraint;


And maybe we should do:

	s/fixed_counter0_constraint/fixed0_constraint/'

Those two constraints only differ by a single character, that's bad for
reading comprehension.

In fact, I just did that too.