Re: [PATCH 4/6] riscv: dts: add initial support for the SiFive FU540-C000 SoC

From: Rob Herring
Date: Thu Apr 11 2019 - 09:10:22 EST

Next message: Joe Perches: "Re: [PATCH RFC] clk: ux500: add range to usleep_range"
Previous message: Flavio Suligoi: "RE: [PATCH 1/2] spi: pxa2xx: fix SCR (divisor) calculation"
In reply to: Paul Walmsley: "[PATCH 4/6] riscv: dts: add initial support for the SiFive FU540-C000 SoC"
Next in thread: Paul Walmsley: "[PATCH 5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

On Thu, Apr 11, 2019 at 3:43 AM Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote:
>
> Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
> Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> Cc: Palmer Dabbelt <palmer@xxxxxxxxxx>
> Cc: Albert Ou <aou@xxxxxxxxxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 207 +++++++++++++++++++++
> 1 file changed, 207 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> new file mode 100644
> index 000000000000..dd3b9395cedf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -0,0 +1,207 @@
> +// SPDX-License-Identifier: (Apache-2.0 OR GPL-2.0+)

You're okay with GPLv9 license?

You're free to license however you want, but most dts files use MIT
for permissive license.

> +/* Copyright (c) 2018-2019 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sifive-fu540-prci.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu540-c000", "sifive,fu540";

No point in this as the board file overrides.

> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <1000000>;
> + cpu0: cpu@0 {
> + compatible = "sifive,e51", "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + reg = <0>;
> + riscv,isa = "rv64imac";
> + status = "okay";

okay is the default.

It is strange cpu@0 is missing many of the cache properties...

> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <1>;
> + riscv,isa = "rv64imafdc";
> + status = "okay";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + clock-frequency = <0>;
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <2>;
> + riscv,isa = "rv64imafdc";
> + status = "okay";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + clock-frequency = <0>;
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <3>;
> + riscv,isa = "rv64imafdc";
> + status = "okay";
> + tlb-split;
> + cpu3_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu4: cpu@4 {
> + clock-frequency = <0>;
> + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <32>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <32>;
> + mmu-type = "riscv,sv39";
> + reg = <4>;
> + riscv,isa = "rv64imafdc";
> + status = "okay";
> + tlb-split;
> + cpu4_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Really need 64-bits of address and size for peripherals?

> + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";

Just simple-bus here. You can't reuse compatible strings.

> + ranges;
> + plic0: interrupt-controller@c000000 {
> + #interrupt-cells = <1>;
> + compatible = "sifive,plic-1.0.0";
> + reg = <0x0 0xc000000 0x0 0x4000000>;
> + interrupt-controller;
> + interrupts-extended = <
> + &cpu0_intc 11
> + &cpu1_intc 11 &cpu1_intc 9
> + &cpu2_intc 11 &cpu2_intc 9
> + &cpu3_intc 11 &cpu3_intc 9
> + &cpu4_intc 11 &cpu4_intc 9>;
> + };
> + prci: clock-controller@10000000 {
> + compatible = "sifive,fu540-c000-prci";
> + reg = <0x0 0x10000000 0x0 0x1000>;
> + clocks = <&hfclk>, <&rtcclk>;
> + #clock-cells = <1>;
> + };
> + uart0: serial@10010000 {
> + compatible = "sifive,fu540-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10010000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;

Move all these up to the parent.

> + interrupts = <4>;
> + clocks = <&prci PRCI_CLK_TLCLK>;
> + };
> + uart1: serial@10011000 {
> + compatible = "sifive,fu540-c000-uart", "sifive,uart0";
> + reg = <0x0 0x10011000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <5>;
> + clocks = <&prci PRCI_CLK_TLCLK>;
> + };
> + qspi0: spi@10040000 {
> + compatible = "sifive,fu540-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10040000 0x0 0x1000
> + 0x0 0x20000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <51>;
> + clocks = <&prci PRCI_CLK_TLCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + qspi2: spi@10050000 {
> + compatible = "sifive,fu540-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10050000 0x0 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <6>;
> + clocks = <&prci PRCI_CLK_TLCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + qspi1: spi@10140000 {
> + compatible = "sifive,fu540-c000-spi", "sifive,spi0";
> + reg = <0x0 0x10140000 0x0 0x1000
> + 0x0 0x30000000 0x0 0x10000000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <52>;
> + clocks = <&prci PRCI_CLK_TLCLK>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> --
> 2.20.1
>

Next message: Joe Perches: "Re: [PATCH RFC] clk: ux500: add range to usleep_range"
Previous message: Flavio Suligoi: "RE: [PATCH 1/2] spi: pxa2xx: fix SCR (divisor) calculation"
In reply to: Paul Walmsley: "[PATCH 4/6] riscv: dts: add initial support for the SiFive FU540-C000 SoC"
Next in thread: Paul Walmsley: "[PATCH 5/6] riscv: dts: add initial board data for the SiFive HiFive Unleashed"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]