Re: [PATCH v5 1/9] clk: mediatek: Disable tuner_en before change PLL rate

[Stephen Boyd]

Quoting Weiyi Lu (2019-03-04 21:05:38)
> From: Owen Chen <owen.chen@xxxxxxxxxxxx>
> 
> PLLs with tuner_en bit, such as APLL1, need to disable
> tuner_en before apply new frequency settings, or the new frequency
> settings (pcw) will not be applied.
> The tuner_en bit will be disabled during changing PLL rate
> and be restored after new settings applied.
> 
> Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
> Cc: <stable@xxxxxxxxxxxxxxx>
> Signed-off-by: Owen Chen <owen.chen@xxxxxxxxxxxx>
> Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
> ---

Applied to clk-next