Re: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off

[Stephen Boyd]

Quoting Weiyi Lu (2019-03-04 21:05:46)
> From: James Liao <jamesjj.liao@xxxxxxxxxxxx>
> 
> Some modules may need to change its clock rate before turn on it.
> So changing PLL's rate when it is off should be allowed.
> This patch removes PLL enabled check before set rate, so that
> PLLs can set new frequency even if they are off.
> 
> On MT8173 for example, ARMPLL's enable bit can be controlled by
> other HW. That means ARMPLL may be turned on even if we (CPU / SW)
> set ARMPLL's enable bit as 0. In this case, SW may want and can
> still change ARMPLL's rate by changing its pcw and postdiv settings.
> But without this patch, new pcw setting will not be applied because
> its enable bit is 0.
> 
> Signed-off-by: James Liao <jamesjj.liao@xxxxxxxxxxxx>
> Acked-by: Michael Turquette <mturuqette@xxxxxxxxxxxx>
> Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
> ---

Applied to clk-next