Re: [RFC v1 1/3] dt-bindings: soc: add mtk svs dt-bindings

[Stephen Boyd]

Quoting Roger Lu (2019-05-07 00:50:57)
> Dear Stephen,
> 
> Sorry for the late reply.
> 
> On Fri, 2019-05-03 at 14:08 -0700, Stephen Boyd wrote:
> > Quoting Roger Lu (2019-05-01 23:19:31)
> > > On Tue, 2019-04-30 at 13:31 -0700, Stephen Boyd wrote:
> > > > Quoting Roger Lu (2019-04-30 04:20:10)
> > > > > diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt
> > > > > new file mode 100644
> > > > > index 000000000000..355329db74ba
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt
> > [..]
> > > > > +
> > > > > +               svs_gpu: svs_gpu {
> > > > > +                       compatible = "mediatek,mt8183-svs-gpu";
> > > > > +                       power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
> > > > > +                       operating-points-v2 = <&gpu_opp_table>;
> > > > > +               };
> > > > 
> > > > It looks like you need multiple OPPs for a single device, because it has
> > > > different independent power supplies it wants to associate the OPP
> > > > tables with?
> > > Yes. SVS has different controllers inside the hardware in order to
> > > calculate and optimize different OPP table voltage part.
> > 
> > So is there more than one SVS register region that needs certain devices
> > to be powered on or at least have their power domain enabled so that the
> > SVS hardware can read the voltage and adjust accordingly? I should read
> > the driver I suppose.
> No, basically, each SVS controller (aka SVS bank) only has one SVS
> register region that needs to be powered on for the init.
> In MT8183 SVS case, SVS has four controllers (banks). Each SVS bank
> needs corresponding power domain to be on for its init.
> 
> #SVS bank corresponding power domain
> svs_cpu_little: Needs CPU-A53 power on for init
> svs_cpu_big: Needs CPU-A73 power on for init
> svs_cci: Needs CPU-A53 power on for init
> svs_gpu: Needs MFG_2D power on for init
> 
> P.S SVS driver will use pm_runtime_get_sync() to turn on power before
> svs bank init and pm_runtime_put_sync() to turn off power power after
> svs bank init.

Ok. How are you making sure that certain CPUs are powered on?

> 
> > 
> > > 
> > > > Why can't these OPP tables be attached to the devices that
> > > > use them, i.e. CPU, GPU, CCI, etc.? Seems odd that those devices don't
> > > > have OPP tables that this hardware block can look up somehow.
> > > Those OPP tables are attached by our DVFS node (please refers below
> > > patch). SVS just shares with their OPP table and help optimize these OPP
> > > tables' voltage part.
> > > 
> > > Add cpufreq DTS node to the mt8183 and mt8183-evb
> > > https://patchwork.kernel.org/patch/10921675/
> > 
> > Cool thanks for the pointer.
> > 
> > > 
> > > 
> > > > Similarly,
> > > > the power domains should probably be part of the devices that are using
> > > > them and not these sub-nodes that are mirroring the other hardware
> > > > blocks in the system?
> > > Oh. There is a svs controller in GPU power-domain. We need to turn on
> > > GPU power so that svs controller can work functionally. Therefore, we
> > > add GPU power-domains in our svs_gpu sub-node.
> > > 
> > > 
> > 
> > Sorry, I'm not really following what you're saying too closely. I think
> > I get it but it sounds complicated.
> > 
> > I'm mostly wondering if having properties like svs-gpu = <&gpu_node>,
> > and svs-cci = <&cci_node> would work for you. The idea would be to link
> > this hardware block to the nodes that it's going to adjust the OPPs of.
> > Once you have the node, use some sort of OPP API to get the OPP table
> > for a device_node and adjust it at runtime for the current OPP.
> Yes, I understand your idea. Thank you. I share my design purpose and
> the troubles I encountered when linking other hardware block.
> 
> #my design purpose
> 1. SVS bank doesn't need all the resources in other device node like
> cci_node. Therefore, I model SVS sub-nodes to declare what svs bank
> needs.

Do you mean that there are other properties in the cci_node that the SVS
hardware block doesn't use? That doesn't sound like a problem to me. I
view nodes in the SoC bus as all memory mapped IO devices and it sounds
like SVS is a hardware IP core that's off to the side in the system that
has some sensors that goes into various other IP blocks in the system.
It's correct to model the registers and interrupts, etc. as one node for
the one hardware block that's delivered by the hardware engineers.

> 
> #troubles - linking other hardware block
> 1. I don't know how to get cpu devcie after we link CPU node
> (svs_cpu_little = <cpu0>). I use "get_cpu_device(unsigned cpu)" in Linux
> driver to attain cpuX device generally.

This should probably be some sort of list property that points to all
the CPUs in the little and big clusters. Then the code can iterate
through the node pointers and look for an OPP table in any of them by
combining of_cpu_node_to_id() with get_cpu_device()?

> 2. Our MT8183 has three gpu-related node as below, svs_gpu need the
> reference of gpu (OPP table) & gpu_core2 (power-domain MFG_2D) to make
> sure svs_gpu can init and update gpu OPP table. I don't know how to
> refer two nodes by one property. Therefore, I model a svs_gpu to declare
> what it needs.
> 
> gpu: mali@13040000 {
>         ...
>         power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_CORE0>;
>         operating-points-v2 = <&gpu_opp_table>;
>         ...
> }
> 
> gpu_core1: mali_gpu_core1 {
>         ...
>         power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_CORE1>;
> };
> 
> gpu_core2: mali_gpu_core2 {
>         ...
>         power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
> };

These three nodes should be combined into one node for the GPU. The
power domains will need to be referred to by name. Luckily we have
support for multiple power domains in the kernel now so this should
work. Let us know if it doesn't work for some reason.

> 
> P.S MT8183 GPU won't do upstream. So, there is no patchwork weblink to
> refer.

Sure.