Re: [PATCH 2/2] powerpc/8xx: Add microcode patch to move SMC parameter RAM.

From: Christophe Leroy
Date: Tue May 14 2019 - 04:37:16 EST

Le 14/05/2019 Ã 10:31, Christophe Leroy a ÃcritÂ:

Le 14/05/2019 Ã 08:56, Michael Ellerman a ÃcritÂ:
Christophe Leroy <christophe.leroy@xxxxxx> writes:

Some SCC functions like the QMC requires an extended parameter RAM.
On modern 8xx (ie 866 and 885), SPI area can already be relocated,
allowing the use of those functions on SCC2. But SCC3 and SCC4
parameter RAM collide with SMC1 and SMC2 parameter RAMs.

This patch adds microcode to allow the relocation of both SMC1 and
SMC2, and relocate them at offsets 0x1ec0 and 0x1fc0.
Those offsets are by default for the CPM1 DSP1 and DSP2, but there
is no kernel driver using them at the moment so this area can be

Signed-off-by: Christophe Leroy <christophe.leroy@xxxxxx>
 arch/powerpc/platforms/8xx/Kconfig | 7 ++
 arch/powerpc/platforms/8xx/micropatch.c | 109 +++++++++++++++++++++++++++++++-
 2 files changed, 114 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/platforms/8xx/micropatch.c b/arch/powerpc/platforms/8xx/micropatch.c
index 33a9042fca80..dc4423daf7d4 100644
--- a/arch/powerpc/platforms/8xx/micropatch.c
+++ b/arch/powerpc/platforms/8xx/micropatch.c
@@ -622,6 +622,86 @@ static uint patch_2f00[] __initdata = {
+ * SMC relocation patch arrays.
+ */
+static uint patch_2000[] __initdata = {
+ÂÂÂ 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000,
+ÂÂÂ 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000,
+ÂÂÂ 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2,

Do we have any doc on what these values are?

No we don't

I get that it's microcode but do we have any more detail than that?
What's the source etc?

There is an Engineering Bulletin (EB662) dated 2006 from Freescale which slightly describe things and there are associated S-Record files containing those values.

Find attached the said doc and files. Not sure it will go through the list. Can't find it on NXP website thought, that must be too old.


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