Re: [PATCH v4 12/15] drm/bridge: tc358767: Introduce tc_pllupdate_pllen()

[Andrzej Hajda]

On 07.06.2019 06:45, Andrey Smirnov wrote:
> tc_wait_pll_lock() is always called as a follow-up for updating
> PLLUPDATE and PLLEN bit of a given PLL control register. To simplify
> things, merge the two operation into a single helper function
> tc_pllupdate_pllen() and convert the rest of the code to use it. No
> functional change intended.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@xxxxxxxxx>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>


I guess tc_pllupdate would be OK as well, but shorter.

Anyway:

Reviewed-by: Andrzej Hajda <a.hajda@xxxxxxxxxxx>

Â--
Regards
Andrzej


> Cc: Archit Taneja <architt@xxxxxxxxxxxxxx>
> Cc: Andrzej Hajda <a.hajda@xxxxxxxxxxx>
> Cc: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
> Cc: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
> Cc: Andrey Gusakov <andrey.gusakov@xxxxxxxxxxxxxxxxxx>
> Cc: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> Cc: Cory Tusar <cory.tusar@xxxxxxxx>
> Cc: Chris Healy <cphealy@xxxxxxxxx>
> Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx
> ---
>  drivers/gpu/drm/bridge/tc358767.c | 30 ++++++++++++++----------------
>  1 file changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
> index ac55b59249e3..c994c72eb330 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -443,10 +443,18 @@ static u32 tc_srcctrl(struct tc_data *tc)
>  	return reg;
>  }
>  
> -static void tc_wait_pll_lock(struct tc_data *tc)
> +static int tc_pllupdate_pllen(struct tc_data *tc, unsigned int pllctrl)
>  {
> +	int ret;
> +
> +	ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
> +	if (ret)
> +		return ret;
> +
>  	/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
>  	usleep_range(3000, 6000);
> +
> +	return 0;
>  }
>  
>  static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
> @@ -546,13 +554,7 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>  		return ret;
>  
>  	/* Force PLL parameter update and disable bypass */
> -	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLUPDATE | PLLEN);
> -	if (ret)
> -		return ret;
> -
> -	tc_wait_pll_lock(tc);
> -
> -	return 0;
> +	return tc_pllupdate_pllen(tc, PXL_PLLCTRL);
>  }
>  
>  static int tc_pxl_pll_dis(struct tc_data *tc)
> @@ -626,15 +628,13 @@ static int tc_aux_link_setup(struct tc_data *tc)
>  	 * Initially PLLs are in bypass. Force PLL parameter update,
>  	 * disable PLL bypass, enable PLL
>  	 */
> -	ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN);
> +	ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL);
>  	if (ret)
>  		goto err;
> -	tc_wait_pll_lock(tc);
>  
> -	ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN);
> +	ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL);
>  	if (ret)
>  		goto err;
> -	tc_wait_pll_lock(tc);
>  
>  	ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
>  	if (ret == -ETIMEDOUT) {
> @@ -914,15 +914,13 @@ static int tc_main_link_enable(struct tc_data *tc)
>  		return ret;
>  
>  	/* PLL setup */
> -	ret = regmap_write(tc->regmap, DP0_PLLCTRL, PLLUPDATE | PLLEN);
> +	ret = tc_pllupdate_pllen(tc, DP0_PLLCTRL);
>  	if (ret)
>  		return ret;
> -	tc_wait_pll_lock(tc);
>  
> -	ret = regmap_write(tc->regmap, DP1_PLLCTRL, PLLUPDATE | PLLEN);
> +	ret = tc_pllupdate_pllen(tc, DP1_PLLCTRL);
>  	if (ret)
>  		return ret;
> -	tc_wait_pll_lock(tc);
>  
>  	/* Reset/Enable Main Links */
>  	dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;