Re: [PATCH 5/5] clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly

[Stephen Boyd]

Quoting Paul Cercueil (2019-05-02 14:25:02)
> The code was setting the bit 21 of the CPCCR register to use a divider
> of 2 for the "pll half" clock, and clearing the bit to use a divider
> of 1.
> 
> This is the opposite of how this register field works: a cleared bit
> means that the /2 divider is used, and a set bit means that the divider
> is 1.
> 
> Restore the correct behaviour using the newly introduced .div_table
> field.
> 
> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> ---

Applied to clk-next