Re: [RFC 1/2] irqchip: irq-imx-gpcv2: Add workaround for i.MX8MQ ERR11171

[Leonard Crestez]

On 6/10/2019 3:15 PM, Abel Vesa wrote:
> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
> breaks cpuidle support due to inability to wake target cores on IPIs.
> 
> Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
> setting 12th bit in IOMUX_GPR1 register. In order to control the target cores
> only, that is, not waking up all the cores every time, we can unmask/mask the
> IRQ 32 in the first GPC IMR register.
> 
> Since EL3 is the one that deals with powering down/up the cores, and since the
> cores wake up in EL3, EL3 should be the one to control the IMRs in this case.
> This implies we need to get into EL3 on every IPI to do the unmasking, leaving
> the masking to be done on the power-up sequence by the core itself.

Manipulating same IMR registers in TF-A and Linux is racy so all IMR 
manipulation (set_wake etc) needs to be done through SIP calls with 
locking inside TF-A.

It would make sense to have an entirely separate SIP-based 
irq-imx8mq-gpc.c driver based on what is used in NXP tree.

> +	iomux_gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (!IS_ERR(iomux_gpr))
> +		regmap_update_bits(iomux_gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
> +					IMX6Q_GPR1_GINT);

Doesn't this initialization belong in TF-A? On boot enable the irq and 
keep it masked until somebody calls "wake".

--
Regards,
Leonard