Re: [PATCH RESEND v3 2/3] KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
From: Xiaoyao Li
Date: Mon Jun 17 2019 - 02:36:21 EST
On 6/17/2019 11:32 AM, Xiaoyao Li wrote:
On 6/16/2019 5:55 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can
reside
in either C0.1 or C0.2.
This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
IA32_UMWAIT_CONTROL between host and guest. The variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu <jingqi.liu@xxxxxxxxx>
Signed-off-by: Jingqi Liu <jingqi.liu@xxxxxxxxx>
Signed-off-by: Tao Xu <tao3.xu@xxxxxxxxx>
---
 arch/x86/kvm/vmx/vmx.c | 36 ++++++++++++++++++++++++++++++++++++
 arch/x86/kvm/vmx/vmx.h | 3 +++
 arch/x86/power/umwait.c | 3 ++-
 3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index b35bfac30a34..f33a25e82cb8 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1679,6 +1679,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu,
struct msr_data *msr_info)
 #endif
ÂÂÂÂÂ case MSR_EFER:
ÂÂÂÂÂÂÂÂÂ return kvm_get_msr_common(vcpu, msr_info);
+ÂÂÂ case MSR_IA32_UMWAIT_CONTROL:
+ÂÂÂÂÂÂÂ if (!vmx_waitpkg_supported())
+ÂÂÂÂÂÂÂÂÂÂÂ return 1;
+
+ÂÂÂÂÂÂÂ msr_info->data = vmx->msr_ia32_umwait_control;
+ÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ case MSR_IA32_SPEC_CTRL:
ÂÂÂÂÂÂÂÂÂ if (!msr_info->host_initiated &&
ÂÂÂÂÂÂÂÂÂÂÂÂÂ !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
@@ -1841,6 +1847,15 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu,
struct msr_data *msr_info)
ÂÂÂÂÂÂÂÂÂÂÂÂÂ return 1;
ÂÂÂÂÂÂÂÂÂ vmcs_write64(GUEST_BNDCFGS, data);
ÂÂÂÂÂÂÂÂÂ break;
+ÂÂÂ case MSR_IA32_UMWAIT_CONTROL:
+ÂÂÂÂÂÂÂ if (!vmx_waitpkg_supported())
+ÂÂÂÂÂÂÂÂÂÂÂ return 1;
+
+ÂÂÂÂÂÂÂ if (!data)
+ÂÂÂÂÂÂÂÂÂÂÂ break;
+
Why cannot clear it to zero?
+ÂÂÂÂÂÂÂ vmx->msr_ia32_umwait_control = data;
+ÂÂÂÂÂÂÂ break;
ÂÂÂÂÂ case MSR_IA32_SPEC_CTRL:
ÂÂÂÂÂÂÂÂÂ if (!msr_info->host_initiated &&
ÂÂÂÂÂÂÂÂÂÂÂÂÂ !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
@@ -4126,6 +4141,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu, bool init_event)
ÂÂÂÂÂ vmx->rmode.vm86_active = 0;
ÂÂÂÂÂ vmx->spec_ctrl = 0;
+ÂÂÂ vmx->msr_ia32_umwait_control = 0;
+
ÂÂÂÂÂ vcpu->arch.microcode_version = 0x100000000ULL;
ÂÂÂÂÂ vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
ÂÂÂÂÂ kvm_set_cr8(vcpu, 0);
@@ -6339,6 +6356,23 @@ static void atomic_switch_perf_msrs(struct
vcpu_vmx *vmx)
ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ msrs[i].host, false);
 }
+static void atomic_switch_ia32_umwait_control(struct vcpu_vmx *vmx)
+{
+ÂÂÂ u64 host_umwait_control;
+
+ÂÂÂ if (!vmx_waitpkg_supported())
+ÂÂÂÂÂÂÂ return;
+
+ÂÂÂ host_umwait_control = umwait_control_cached;
+
It's redundant to define host_umwait_control and this line, we can just
use umwait_control_cached.
+ÂÂÂ if (vmx->msr_ia32_umwait_control != host_umwait_control)
+ÂÂÂÂÂÂÂ add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ vmx->msr_ia32_umwait_control,
+ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ host_umwait_control, false);
The bit 1 is reserved, at least, we need to do below to ensure not
modifying the reserved bit:
ÂÂÂÂguest_val = (vmx->msr_ia32_umwait_control & ~BIT_ULL(1)) |
ÂÂÂÂÂÂÂÂÂÂÂ (host_val & BIT_ULL(1))
I find a better solution to ensure reserved bit 1 not being modified in
vmx_set_msr() as below:
if((data ^ umwait_control_cached) & BIT_ULL(1))
return 1;
+ÂÂÂ else
+ÂÂÂÂÂÂÂ clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL);
+}
+
 static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
 {
ÂÂÂÂÂ vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
@@ -6447,6 +6481,8 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
ÂÂÂÂÂ atomic_switch_perf_msrs(vmx);
+ÂÂÂ atomic_switch_ia32_umwait_control(vmx);
+
ÂÂÂÂÂ vmx_update_hv_timer(vcpu);
ÂÂÂÂÂ /*
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index 61128b48c503..8485bec7c38a 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -14,6 +14,8 @@
 extern const u32 vmx_msr_index[];
 extern u64 host_efer;
+extern u32 umwait_control_cached;
+
 #define MSR_TYPE_R 1
 #define MSR_TYPE_W 2
 #define MSR_TYPE_RW 3
@@ -194,6 +196,7 @@ struct vcpu_vmx {
 #endif
ÂÂÂÂÂ u64ÂÂÂÂÂÂÂÂÂÂÂÂÂ spec_ctrl;
+ÂÂÂ u64ÂÂÂÂÂÂÂÂÂÂÂÂÂ msr_ia32_umwait_control;
ÂÂÂÂÂ u32 vm_entry_controls_shadow;
ÂÂÂÂÂ u32 vm_exit_controls_shadow;
diff --git a/arch/x86/power/umwait.c b/arch/x86/power/umwait.c
index 7fa381e3fd4e..2e6ce4cbccb3 100644
--- a/arch/x86/power/umwait.c
+++ b/arch/x86/power/umwait.c
@@ -9,7 +9,8 @@
ÂÂ * MSR value. By default, umwait max time is 100000 in TSC-quanta
and C0.2
ÂÂ * is enabled
ÂÂ */
-static u32 umwait_control_cached = 100000;
+u32 umwait_control_cached = 100000;
+EXPORT_SYMBOL_GPL(umwait_control_cached);
 /*
ÂÂ * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL
MSR