RE: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors

[Z.q. Hou]

Hi Lorenzo,

> -----Original Message-----
> From: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
> Sent: 2019å6æ17æ 17:29
> To: Z.q. Hou <zhiqiang.hou@xxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx;
> l.subrahmanya@xxxxxxxxxxxxxx; shawnguo@xxxxxxxxxx; Leo Li
> <leoyang.li@xxxxxxx>; catalin.marinas@xxxxxxx; will.deacon@xxxxxxx;
> Mingkai Hu <mingkai.hu@xxxxxxx>; M.h. Lian <minghuan.lian@xxxxxxx>;
> Xiaowei Bao <xiaowei.bao@xxxxxxx>
> Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register
> accessors
> 
> On Sat, Jun 15, 2019 at 01:13:48AM +0000, Z.q. Hou wrote:
> > Hi Lorenzo,
> >
> > > -----Original Message-----
> > > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@xxxxxxx]
> > > Sent: 2019å6æ12æ 21:54
> > > To: Z.q. Hou <zhiqiang.hou@xxxxxxx>
> > > Cc: linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> > > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> > > bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx;
> > > l.subrahmanya@xxxxxxxxxxxxxx; shawnguo@xxxxxxxxxx; Leo Li
> > > <leoyang.li@xxxxxxx>; catalin.marinas@xxxxxxx;
> will.deacon@xxxxxxx;
> > > Mingkai Hu <mingkai.hu@xxxxxxx>; M.h. Lian
> <minghuan.lian@xxxxxxx>;
> > > Xiaowei Bao <xiaowei.bao@xxxxxxx>
> > > Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit
> > > register accessors
> > >
> > > On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote:
> > > > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > > >
> > > > There are some 8-bit and 16-bit registers in PCIe configuration
> > > > space, so add accessors for them.
> > > >
> > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > > > Reviewed-by: Minghuan Lian <Minghuan.Lian@xxxxxxx>
> > > > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@xxxxxxxxxxxxxx>
> > > > ---
> > > > V5:
> > > >  - Corrected and retouched the subject and changelog.
> > > >  - No functionality change.
> > > >
> > > >  drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
> > > >  1 file changed, 20 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > > > b/drivers/pci/controller/pcie-mobiveil.c
> > > > index 411e9779da12..456adfee393c 100644
> > > > --- a/drivers/pci/controller/pcie-mobiveil.c
> > > > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > > > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie
> > > > *pcie,
> > > u32 off)
> > > >  	return csr_read(pcie, off, 0x4);  }
> > > >
> > > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) {
> > > > +	return csr_read(pcie, off, 0x2); }
> > > > +
> > > > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) {
> > > > +	return csr_read(pcie, off, 0x1); }
> > > > +
> > > >  static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32
> > > > off) {
> > > >  	csr_write(pcie, val, off, 0x4);
> > > >  }
> > > >
> > > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32
> > > > +off) {
> > > > +	csr_write(pcie, val, off, 0x2);
> > > > +}
> > > > +
> > > > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32
> > > > +off) {
> > > > +	csr_write(pcie, val, off, 0x1);
> > > > +}
> > > > +
> > >
> > > They are not used so you should drop this patch.
> >
> > NXP Layerscape PCIe Gen4 controller driver will use them, so don't
> > drop it.
> 
> You add functions when they are needed, so drop this patch and squash it to
> the patch that use these functions.
>

Yes, agree, please drop it from this patch set.
 
Thanks,
Zhiqiang

> Lorenzo
> 
> > Thanks,
> > Zhiqiang
> >
> > >
> > > Lorenzo
> > >
> > > >  static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  {
> > > >  	return (csr_readl(pcie, LTSSM_STATUS) &
> > > > --
> > > > 2.17.1
> > > >