Re: [PATCH] drm: Permit video-buffers writecombine mapping for MIPS
From: Serge Semin
Date: Fri Jun 21 2019 - 02:07:58 EST
Hello Sean,
On Tue, Jun 18, 2019 at 03:52:04PM -0400, Sean Paul wrote:
> On Mon, Jun 17, 2019 at 04:47:30PM +0300, Serge Semin wrote:
> > Hello folks,
> >
> > Any updates of this patch status? It has been here for about two months.
> >
>
> Sorry for the mixup, looks like this one just fell through the cracks. I've
> applied it to drm-misc-next with the attached Ack and Review.
>
Great! Thank you.
Regards,
-Sergey
> Sean
>
>
> > Regards,
> > -Sergey
> >
> > On Tue, Apr 23, 2019 at 03:31:22PM +0300, Serge Semin wrote:
> > > Since commit 4b050ba7a66c ("MIPS: pgtable.h: Implement the
> > > pgprot_writecombine function for MIPS") and commit c4687b15a848 ("MIPS: Fix
> > > definition of pgprot_writecombine()") write-combine vma mapping is
> > > available to be used by kernel subsystems for MIPS. In particular the
> > > uncached accelerated attribute is requested to be set by ioremap_wc()
> > > method and by generic PCI memory pages/ranges mapping methods. The same
> > > is done by the drm_io_prot()/ttm_io_prot() functions in case if
> > > write-combine flag is set for vma's passed for mapping. But for some
> > > reason the pgprot_writecombine() method calling is ifdefed to be a
> > > platform-specific with MIPS system being marked as lacking of one. At the
> > > very least it doesn't reflect the current MIPS platform implementation.
> > > So in order to improve the DRM subsystem performance on MIPS with UCA
> > > mapping enabled, we need to have pgprot_writecombine() called for buffers,
> > > which need store operations being combined. In case if particular MIPS
> > > chip doesn't support the UCA attribute, the mapping will fall back to
> > > noncached.
> > >
> > > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> > > Cc: Paul Burton <paul.burton@xxxxxxxx>
> > > Cc: James Hogan <jhogan@xxxxxxxxxx>
> > > Signed-off-by: Vadim V. Vlasov <vadim.vlasov@xxxxxxxxxxxxxx>
> > > Signed-off-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/drm_vm.c | 5 +++--
> > > drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++--
> > > 2 files changed, 5 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
> > > index c3301046dfaa..50178dc64060 100644
> > > --- a/drivers/gpu/drm/drm_vm.c
> > > +++ b/drivers/gpu/drm/drm_vm.c
> > > @@ -62,7 +62,8 @@ static pgprot_t drm_io_prot(struct drm_local_map *map,
> > > /* We don't want graphics memory to be mapped encrypted */
> > > tmp = pgprot_decrypted(tmp);
> > >
> > > -#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__)
> > > +#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc__) || \
> > > + defined(__mips__)
> > > if (map->type == _DRM_REGISTERS && !(map->flags & _DRM_WRITE_COMBINING))
> > > tmp = pgprot_noncached(tmp);
> > > else
> > > @@ -73,7 +74,7 @@ static pgprot_t drm_io_prot(struct drm_local_map *map,
> > > tmp = pgprot_writecombine(tmp);
> > > else
> > > tmp = pgprot_noncached(tmp);
> > > -#elif defined(__sparc__) || defined(__arm__) || defined(__mips__)
> > > +#elif defined(__sparc__) || defined(__arm__)
> > > tmp = pgprot_noncached(tmp);
> > > #endif
> > > return tmp;
> > > diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
> > > index 895d77d799e4..9f918b992f7e 100644
> > > --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
> > > +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
> > > @@ -539,13 +539,13 @@ pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp)
> > > tmp = pgprot_noncached(tmp);
> > > #endif
> > > #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> > > - defined(__powerpc__)
> > > + defined(__powerpc__) || defined(__mips__)
> > > if (caching_flags & TTM_PL_FLAG_WC)
> > > tmp = pgprot_writecombine(tmp);
> > > else
> > > tmp = pgprot_noncached(tmp);
> > > #endif
> > > -#if defined(__sparc__) || defined(__mips__)
> > > +#if defined(__sparc__)
> > > tmp = pgprot_noncached(tmp);
> > > #endif
> > > return tmp;
> > > --
> > > 2.21.0
> > >
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS