Re: [RFC] perf/x86/intel: Disable check_msr for real hw

[Jiri Olsa]

On Mon, Jun 24, 2019 at 09:46:17AM -0700, Andi Kleen wrote:
> > > The other hypervisors are relatively obscure, but eventually
> > > someone will hit problems.
> > 
> > any idea if there's any other flag/way we could use to detect those?
> 
> I'm not aware of a generic way to detect any hypervisor unfortunately.
> 
> There are hypervisor reserved cpuid ranges, in theory you could
> probe the existence of those. But there might be always some which
> don't have extra CPUIDs.
> 
> > 
> > adding few virtualization folks to the loop
> > and attaching the original patch
> > 
> > thanks,
> > jirka
> > 
> > 
> > ---
> > Tom Vaden reported false failure of check_msr function, because
> > some servers can do POST tracing and enable LBR tracing during
> > the boot.
> 
> Just to understand the original problem, the LBR registers
> get locked somehow? It would be reasonable to not use LBRs
> in this case. We just need to make sure everything 
> else is still probed.

Tom, plz correctme if I'm wrongm but AFAIK because the LBR tracing is
enabled during the boot the lbr_from/lbr_to registers will fail the
check_msr 'val_new != val_tmp' check

if there's no good way to detect this, maybe we add boot option
to disable the check_msr check

jirka